-
1
-
-
37549032725
-
IBM POWER6 microarchitecture
-
Nov.
-
H. Q. Le, W. J. Starke, J. S. Fields, F. P. O'Connell, D. Q. Nguyen, B. J. Ronchetti, W. M. Sauer, E. M. Schwarz, and M. T. Vaden, "IBM POWER6 microarchitecture," IBM Journal of Research and Development, vol. 51, no. 6, pp. 639-662, Nov. 2007.
-
(2007)
IBM Journal of Research and Development
, vol.51
, Issue.6
, pp. 639-662
-
-
Le, H.Q.1
Starke, W.J.2
Fields, J.S.3
O'Connell, F.P.4
Nguyen, D.Q.5
Ronchetti, B.J.6
Sauer, W.M.7
Schwarz, E.M.8
Vaden, M.T.9
-
2
-
-
51349168284
-
UltraSPARC T2: A highly-threaded, power-efficient, SPARC SoC
-
M. Shah, et al, "UltraSPARC T2: A highly-threaded, power-efficient, SPARC SoC," in IEEE Asian Solid-State Circuits Conference, Nov. 2007, pp. 22-25.
-
IEEE Asian Solid-State Circuits Conference, Nov. 2007
, pp. 22-25
-
-
Shah, M.1
-
3
-
-
44349142233
-
Integration challenges and tradeoffs for tera-scale architectures
-
Aug.
-
M. Azimi, et al, "Integration challenges and tradeoffs for tera-scale architectures," Intel Technology Journal, vol. 11, no. 3, pp. 173-184, Aug. 2007.
-
(2007)
Intel Technology Journal
, vol.11
, Issue.3
, pp. 173-184
-
-
Azimi, M.1
-
4
-
-
34548817260
-
The implementation of the 65nm dual-core 64b merom processor
-
N. Sakran, M. Uffe, M. Mehelel, J. Dowweck, E. Knoll, and A. Kovacks, "The implementation of the 65nm dual-core 64b merom processor," in IEEE Int'l Solid-State Circuits Conference (ISSCC), Feb. 2007, pp. 106-590.
-
IEEE Int'l Solid-State Circuits Conference (ISSCC), Feb. 2007
, pp. 106-590
-
-
Sakran, N.1
Uffe, M.2
Mehelel, M.3
Dowweck, J.4
Knoll, E.5
Kovacks, A.6
-
5
-
-
0036949388
-
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
-
C. Kim, D. Burger, and S. W. Keckler, "An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches," in 10th Int. Conf. on Architectural Support for Programming Language and Operating Systems (ASPLOS), Oct. 2002, pp. 211-222.
-
10th Int. Conf. on Architectural Support for Programming Language and Operating Systems (ASPLOS), Oct. 2002
, pp. 211-222
-
-
Kim, C.1
Burger, D.2
Keckler, S.W.3
-
6
-
-
32844471317
-
A NUCA substrate for flexible CMP cache sharing
-
J. Huh, C. Kim, H. Shafi, L. Zhang, D. Burger, and S. W. Keckler, "A NUCA substrate for flexible CMP cache sharing," in 19th Int'l Conference on Supercomputing (ICS), Jun. 2005, pp. 31-40.
-
19th Int'l Conference on Supercomputing (ICS), Jun. 2005
, pp. 31-40
-
-
Huh, J.1
Kim, C.2
Shafi, H.3
Zhang, L.4
Burger, D.5
Keckler, S.W.6
-
9
-
-
40349095122
-
Managing distributed, shared L2 caches through OS-level page allocation
-
S. Cho and L. Jin, "Managing distributed, shared L2 caches through OS-level page allocation," in 39th IEEE/ACM Int'l Symp. on Microarchitecture (MICRO), Dec. 2006, pp. 455-465.
-
39th IEEE/ACM Int'l Symp. on Microarchitecture (MICRO), Dec. 2006
, pp. 455-465
-
-
Cho, S.1
Jin, L.2
-
10
-
-
22944440036
-
High-performance throughput computing
-
May
-
S. Chaudhry, P. Caprioli, S. Yip, and M. Tremblay, "High-performance throughput computing," IEEE Micro, vol. 25, no. 3, pp. 32-45, May 2005.
-
(2005)
IEEE Micro
, vol.25
, Issue.3
, pp. 32-45
-
-
Chaudhry, S.1
Caprioli, P.2
Yip, S.3
Tremblay, M.4
-
11
-
-
2942639675
-
Technology, performance, and computer-aided design of three-dimensional integrated circuits
-
S. Das, A. Fan, K.-N. Chen, C. S. Tan, N. Checka, and R. Reif, "Technology, performance, and computer-aided design of three-dimensional integrated circuits," in Int'l Symposium on Physical Design, Apr. 2004, pp. 108-115.
-
Int'l Symposium on Physical Design, Apr. 2004
, pp. 108-115
-
-
Das, S.1
Fan, A.2
Chen, K.-N.3
Tan, C.S.4
Checka, N.5
Reif, R.6
-
13
-
-
0036469676
-
Simics: A full system simulation platform
-
Feb.
-
P. S. Magnusson, et al, "Simics: A full system simulation platform," IEEE Computer, vol. 35, no. 2, pp. 50-58, Feb. 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnusson, P.S.1
-
14
-
-
33748870886
-
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
-
Sep.
-
M. M. Martin, et al, "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," Computer Architecture News, vol. 33, no. 4, pp. 92-99, Sep. 2005.
-
(2005)
Computer Architecture News
, vol.33
, Issue.4
, pp. 92-99
-
-
Martin, M.M.1
-
15
-
-
0037643684
-
SICOSYS: An integrated framework for studying interconnection network in multiprocessor systems
-
V. Puente, J. A. Gregorio, and R. Beivide, "SICOSYS: An integrated framework for studying interconnection network in multiprocessor systems," in 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, Jan. 2002, pp. 15-22.
-
10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, Jan. 2002
, pp. 15-22
-
-
Puente, V.1
Gregorio, J.A.2
Beivide, R.3
-
16
-
-
67649661466
-
-
HP Labs, Tech. Rep. HPL-2008-2020, Apr.
-
S. Thoziyoor, N. Muralimanohar, J. H. Ahn, and N. P. Jouppi, "Cacti 5.1," HP Labs, Tech. Rep. HPL-2008-2020, Apr. 2008.
-
(2008)
Cacti 5.1
-
-
Thoziyoor, S.1
Muralimanohar, N.2
Ahn, J.H.3
Jouppi, N.P.4
-
17
-
-
0029194459
-
The SPLASH-2 programs: Characterization and methodological considerations
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations," in 22nd Int'l Symp. on Computer Architecture (ISCA), Jun. 1995, pp. 24-36.
-
22nd Int'l Symp. on Computer Architecture (ISCA), Jun. 1995
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
18
-
-
0029192463
-
Efficient support for irregular applications on distributedmemory machines
-
S. S. Mukherjee, S. D. Sharma, M. D. Hill, J. R. Larus, A. Rogers, and J. Saltz, "Efficient support for irregular applications on distributedmemory machines," in 5th Int'l Symp. on Principles & Practice of Parallel Programming (PPoPP), Jul. 1995, pp. 68-79.
-
5th Int'l Symp. on Principles & Practice of Parallel Programming (PPoPP), Jul. 1995
, pp. 68-79
-
-
Mukherjee, S.S.1
Sharma, S.D.2
Hill, M.D.3
Larus, J.R.4
Rogers, A.5
Saltz, J.6
-
20
-
-
84944411840
-
Distance associativity for high-performance energy-efficient non-uniform cache architectures
-
Z. Chishti, M. D. Powell, and T. N. Vijaykumar, "Distance associativity for high-performance energy-efficient non-uniform cache architectures," in 36th IEEE/ACM Int'l Symp. on Microarchitecture (MICRO), Dec. 2003, pp. 55-66.
-
36th IEEE/ACM Int'l Symp. on Microarchitecture (MICRO), Dec. 2003
, pp. 55-66
-
-
Chishti, Z.1
Powell, M.D.2
Vijaykumar, T.N.3
-
23
-
-
57749186047
-
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
-
J. Lin, Q. Lu, X. Ding, Z. Zhang, X. Zhang, and P. Sadayappan, "Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems," in 14th Int'l Symp. on High-Performance Computer Architecture (HPCA), Feb. 2008, pp. 367-378.
-
14th Int'l Symp. on High-Performance Computer Architecture (HPCA), Feb. 2008
, pp. 367-378
-
-
Lin, J.1
Lu, Q.2
Ding, X.3
Zhang, Z.4
Zhang, X.5
Sadayappan, P.6
-
24
-
-
64949140362
-
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
-
M. Awasthi, K. Sudan, R. Balasubramonian, and J. Carter, "Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches," in 15th Int'l Symp. on High-Performance Computer Architecture (HPCA), Feb. 2009, pp. 250-261.
-
15th Int'l Symp. on High-Performance Computer Architecture (HPCA), Feb. 2009
, pp. 250-261
-
-
Awasthi, M.1
Sudan, K.2
Balasubramonian, R.3
Carter, J.4
|