A 60GHz-band 2x2 phased-array transmitter in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 42-43

  Chan, Wei L ^a   Long, John R ^a   Spirito, Marco ^a   Pekarik, John J ^b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANTENNA GAINS; BASE-BAND CIRCUITRY; BULK CMOS; COINTEGRATION; COLLISION AVOIDANCE RADAR; FULLY-DIFFERENTIAL; GHZ BAND; HORIZONTAL POLARIZATION; MM-WAVE APPLICATION; PATH LOSS; PHASED ARRAY ANTENNAS; PHASED ARRAYS; PHASED-ARRAY TRANSMITTER; PRODUCTION COST; RADIATED POWER; RADIATING ELEMENTS; RADIO IMAGING; SPATIAL SELECTIVITY; STAND -ALONE;

ANTENNAS; CMOS INTEGRATED CIRCUITS; RADAR IMAGING;

TRANSMITTERS;

EID: 77952135246     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434058     Document Type: Conference Paper

References (6)

1. H. Krishnaswamy and H. Hashemi, "A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable-Phase Ring Oscillator and PLL Architecture," ISSCC Dig. Tech. Papers, pp. 124-125, Feb., 2007.
2. A. Natarajan, A. Komijani, X. Guan, A. Babakhani et al., "A 77-GHz Phased-Array Transmitter With LO-Path Phase Shifting in Silicon," ISSCC Dig. Tech. Papers, pp. 182-183, Feb., 2006.
3. S.-Y. Hsiao and C.-Y. Wu, "A Parallel Structure for CMOS Four-Quadrant Analog Multipliers and its Application to a 2-GHz RF Downconversion Mixer," IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 859-869, June 1998.
4. W. L. Chan and J. R. Long, "A 56-65 GHz Injection-Locked Frequency Tripler with Quadrature Outputs in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2739-2746, Dec. 2008.
5. W. L. Chan, J. R. Long, M. Spirito and J. J. Pekarik, "A 60GHz band, 1V 11.5 dBm Power Amplifier with 11% PAE in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 380-381, Feb., 2009.
6. Z. Luo, A. Steegen, M. Eller, R. Mann et al., "High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS Technology," IEDM Dig. Tech Papers, pp. 661-664, Dec., 2004.