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Volumn , Issue , 2009, Pages 2867-2873

Model-based development of MPSoCs with support for early validation

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SCENARIO; BEHAVIORAL MODEL; BEHAVIORAL SPECIFICATION; CONTROL LOOP; CONTROL LOOP STABILITY; DEVELOPMENT PROCESS; IMPLEMENTATION MODELS; IP CORE; LEVEL OF ABSTRACTION; MODEL BASED DEVELOPMENT; MULTIPROCESSOR-SYSTEM; NETWORK-ON-A-CHIP; SEAMLESS SYSTEM; SINGLE CHIPS; SYSTEMC; TIME DOMAIN; TOOL SUPPORT;

EID: 77951616726     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2009.5415397     Document Type: Conference Paper
Times cited : (9)

References (12)
  • 2
    • 77951609873 scopus 로고    scopus 로고
    • Tera-scale computing
    • M. Azimi and et al., "Tera-scale computing," Intel Technology Journal, vol.11, no.3, 2007.
    • (2007) Intel Technology Journal , vol.11 , Issue.3
    • Azimi, M.1
  • 3
    • 77951611518 scopus 로고    scopus 로고
    • International roadmap of semiconductors
    • 2007 edition, section design,"
    • "International roadmap of semiconductors - 2007 edition, section design," SIA, Tech. Rep.
    • SIA, Tech. Rep.
  • 8
    • 77951615865 scopus 로고    scopus 로고
    • Master's thesis, Vienna University of Technology, Faculty of Computer Science, Real-Time Systems Group
    • G. Engleder, "Time-triggered network-on-a-chip," Master's thesis, Vienna University of Technology, Faculty of Computer Science, Real-Time Systems Group, 2007.
    • (2007) Time-triggered Network-on-a-chip
    • Engleder, G.1
  • 12


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.