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Volumn , Issue , 2010, Pages 229-238
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Degradation in FPGAs: Measurement and modelling
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Author keywords
FPGA; Self test
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Indexed keywords
ACCELERATED LIFE TESTS;
CIRCUIT DENSITY;
DEGRADATION MECHANISM;
EXPECTED EFFECTS;
GRADUAL DEGRADATION;
HOT CARRIER INJECTION;
NEGATIVE BIAS TEMPERATURE INSTABILITY;
PROCESS SCALING;
REGULAR STRUCTURE;
RELIABILITY ENHANCEMENT;
SELF TEST;
SHRINKING GEOMETRIES;
SYSTEM LEVELS;
TIMING PERFORMANCE;
VLSI TECHNOLOGY;
DEGRADATION;
FIELD EFFECT TRANSISTORS;
HOT CARRIERS;
LOGIC GATES;
TESTING;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
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EID: 77951583090
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/1723112.1723152 Document Type: Conference Paper |
Times cited : (83)
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References (9)
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