High memory throughput FPGA architecture for high-definition belief-propagation stereo matching

3rd International Conference on Signals, Circuits and Systems, SCS 2009

Volumn , Issue , 2009, Pages

  Pérez, Jesús M ^a   Sánchez, Pablo ^a   Martínez, Marcos ^b  

^a UNIVERSITY OF CANTABRIA   (Spain)

^b Parc Tecnológic ^*  (Spain)

Author keywords

Belief propagation; Depth estimation; FPGA; High definition; Stereo matching

Indexed keywords

3D SYSTEMS; BELIEF PROPAGATION; D-ALGORITHM; DEPTH ESTIMATION; DEPTH MAP; EXECUTION TIME; FPGA ARCHITECTURES; FPGA IMPLEMENTATIONS; HIGH DEFINITION; INHERENT PARALLELISM; ITERATIVE PROCESS; MAXIMUM FREQUENCY; REAL APPLICATIONS; STEREO MATCHING; STEREOSCOPIC IMAGE;

DATA FLOW ANALYSIS; ESTIMATION; MESSAGE PASSING; PROGRAM PROCESSORS; THREE DIMENSIONAL;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77951486617     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSCS.2009.5412615     Document Type: Conference Paper

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