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Volumn 54, Issue 3, 2007, Pages 1800-1804
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A hardware accelerator and FPGA realization for reduced visibility graph construction using efficient bit representations
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Author keywords
Efficient bit representation; Field programmable gate array (FPGA) implementation; Hardware accelerator; Reduced visibility graph (RVG); Robotics
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Indexed keywords
FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS;
HARDWARE ACCELERATORS;
INTERSECTION POINTS;
RANDOM ACCESS MEMORIES;
REDUCED VISIBILITY;
REDUCED VISIBILITY GRAPH (RVG);
SHORTEST PATH;
COMPUTATIONAL COMPLEXITY;
LOGIC GATES;
RANDOM ACCESS STORAGE;
ROBOTICS;
ROBOTS;
UNMANNED AERIAL VEHICLES (UAV);
VISIBILITY;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
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EID: 77951170753
PISSN: 02780046
EISSN: None
Source Type: Journal
DOI: 10.1109/TIE.2007.894726 Document Type: Article |
Times cited : (12)
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References (10)
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