Empirical performance models for 3T1D memories

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 398-403

  Lovin, Kristen ^a   Lee, Benjamin C ^b   Liang, Xiaoyao ^c   Brooks, David ^d   Wei, Gu Yeon ^d  

^a MICROSOFT   (United States)

^b STANFORD UNIVERSITY   (United States)

^c Suzhou University   (United States)

^d HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; CRITICAL PATHS; DRAM CELLS; EMPIRICAL PERFORMANCE; MEDIAN ERRORS; MEMORY ARCHITECTURE; MEMORY ARRAY; MEMORY CELL; MEMORY CELL DESIGN; MONTE CARLO; MONTE CARLO DATA; PERFORMANCE MODEL; PROCESS VARIATION; REGRESSION MODEL; SIMULATION TIME;

MONTE CARLO METHODS; REGRESSION ANALYSIS; SEMICONDUCTOR STORAGE;

DESIGN;

EID: 77951004568     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413124     Document Type: Conference Paper

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