Encapsulation challenges for wafer level packaging

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 903-908

  Eric Kuah, T H ^a   Hao, J Y ^c   Ding, J P ^c   Li, Q F ^c   Chan, W L ^c   Ho, S C ^c   Huang, H M ^b   Jiang, Y J ^b  

^a ASM Technology Singapore Pte Ltd   (Singapore)

^b SILICONWARE PRECISION INDUSTRIES CO LTD   (Taiwan)

^c NONE

Author keywords

Co planarity; Die Shift (DS); Mold Bleed Flashing (MBF); PEMs (plastic encapsulated microelectronics); Tape crinkle incomplete filling; Voiding; Wafer Level Molding (WLM); Warpage; WLP (Wafer Level Package)

Indexed keywords

CO-PLANARITY; PEMS (PLASTIC ENCAPSULATED MICROELECTRONICS); VOIDING; WAFER LEVEL; WAFER LEVEL PACKAGE; WARPAGE; WARPAGES;

DIELECTRIC RELAXATION; DIES; MICROELECTRONICS; MOLDING; MOLDS; PACKAGING; SILICONES; THERMAL EXPANSION;

ELECTRONICS PACKAGING;

EID: 77950949761     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416414     Document Type: Conference Paper

References (2)

1. S. C. Johnson, "Fan-out wafer-level packages catch on", 3D Packaging News Letter on 3D IC, TSV, WLP and embedded Technologies, Issue 10, March 2009.
2. rd International Electronics Manufacturing Technology Conference 2008.