Designing energy-efficient low-diameter on-chip networks with equalized interconnects

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects

Volumn , Issue , 2009, Pages 3-7

  Joshi, Ajay ^a   Kim, Byungsub ^a   Stojanović, Vladimir ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENT; GLOBAL COMMUNICATION; HIGH THROUGHPUT; LOW LATENCY; LOW-DIAMETER NETWORKS; MINIMIZING ENERGY; MULTI-CORE SYSTEMS; ON-CHIP COMMUNICATION NETWORKS; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; PROGRAMMER PRODUCTIVITY; TRAFFIC PATTERN; VIRTUAL CHANNELS; WIRE AREA; WIRE CHANNELS;

COMMUNICATION; COMMUNICATION CHANNELS (INFORMATION THEORY);

WIRE;

EID: 77950938864     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HOTI.2009.13     Document Type: Conference Paper

References (0)