Alignment and overlay characterization for 3d integration and advanced packaging

Proceedings of the Electronic Packaging Technology Conference, EPTC

Volumn , Issue , 2009, Pages 447-451

  V Zeijl, H W ^a   Sarro, P M ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ADVANCED PACKAGING; ALIGNMENT SYSTEM; ETCH PROCESS; OVERLAY ACCURACY; THROUGH SILICON VIAS; WAFER LEVEL PACKAGING; WAFER-THINNING PROCESS; WLP PROCESS;

ALIGNMENT; PACKAGING; SILICON WAFERS; THICK FILMS; THREE DIMENSIONAL; WAFER BONDING;

ELECTRONICS PACKAGING;

EID: 77950934816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416504     Document Type: Conference Paper

References (8)

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4. H. W. van Zeijl, et. al., "Front - to Backwafer Overlay Accuracy in Substrate Transfer Technologies", Proceedings of the 1st international conference on semiconductor technology, The electrochemical society, Vol.2001-17, May 2001, pp 356-367
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6. H. W. van Zeijl, et. al. ,"Waferstepper Alignment for MEMS Applications using Diffraction ratings", MRS Symposium Proc. Vol.729 - BioMEMS and Bionanotechnology, 1-3 April 2002..
7. H.W. van Zeijl, et. al., "Characterization Waferstepper and Process Related Front- to Backwafer Overlay Errors in Bulk Micro Machining using Electrical Overlay Test Structures", Proc. SPIE, MEMS, MOEMS and Micromachining, Vol.5455, April 2004
8. N. Launay, et. al., "Design and characterization of a novel icp plasma tool for high speed and high accuracy drie processing", Proc. IEEE MEMS 2008, Tucson, Arizona, USA, Jan 13-17, 2008, pp.311-314