Standby leakage power reduction technique for nanoscale CMOS VLSI systems

IEEE Transactions on Instrumentation and Measurement

Volumn 59, Issue 5, 2010, Pages 1127-1133

  Jeon, Heungjun ^a   Kim, Yong Bin ^a   Choi, Minsu ^b  

^a Northeastern University   (United States)

^b Architectural and Environmental Engineering   (United States)

Author keywords

Band to band tunneling (BTBT) leakage; Gate leakage; Leakage current; Leakage power; Optimal body bias voltage; Subthreshold leakage

Indexed keywords

BAND TO BAND TUNNELING; BODY BIAS; GATE LEAKAGE; GATE LEAKAGES; SUB-THRESHOLD LEAKAGE;

BIAS VOLTAGE; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; NANOSTRUCTURED MATERIALS; OPTIMIZATION; STANDBY POWER SYSTEMS; TUNNELING (EXCAVATION); WIND TUNNELS;

LEAKAGE CURRENTS;

EID: 77950917678     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2010.2044710     Document Type: Conference Paper

References (17)

1. ITRS. 2007 edition.
2. D. A. Antoniadis, I. Aberg, C. N. Chléirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt, "Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations," IBM J. Res. Develop., vol.50, no.4, pp. 363-376, Jul. 2006. (Pubitemid 44364159)
3. D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H.-S. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol.89, no.3, pp. 259-288, Mar. 2001. (Pubitemid 33766576)
4. M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, "Scaling, power, and the future of CMOS," in IEDM Tech. Dig., Dec. 5, 2005, pp. 7-15.
5. W. R. Tonti, "MOS technology drivers," IEEE Trans. Device Mater. Rel., vol.8, no.2, pp. 406-415, Jun. 2008.
6. C. Neau and K. Roy, "Optimal body bias selection for leakage improvement and process compensation over different technology generations," in Proc. ISLEP, Aug. 2003, pp. 116-121.
7. J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," in Proc. ISSCC, 2002, pp. 786-789.
8. M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y. Hagihara, "Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes," IEEE J. Solid-State Circuits, vol.41, no.4, pp. 805- 814, Apr. 2006.
9. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits," Proc. IEEE, vol.91, no.2, pp. 305-327, Feb. 2003. (Pubitemid 43779250)
10. B. Razavi, Design of Analog CMOS Integrated Circuits, 1st ed. New York: McGraw-Hill, 2001.
11. S. A. Parke, J. E. Moon, H. C. Wann, P. K. Ko, and C. Hu, "Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model," IEEE Trans. Electron Devices, vol.39, no.7, pp. 1694-1703, Jul. 1992.
12. X. Yuan, J. E. Park, J. Wang, E. Zhao, D. C. Ahlgren, T. Hook, J. Yuan, V. Chan, H. Shang, C.-H. Liang, R. Lindsay, S. Park, and H. Choo, "Gateinduced- drain-leakage current in 45-nm CMOS technology," in Proc. IRW, 2007, pp. 70-73.
13. P. J. Wright and K. C. Saraswat, "Thickness limitations of SiO2 gate dielectrics for MOS ULSI," IEEE Trans. Electron Devices, vol.37, no.8, pp. 1884-1892, Aug. 1990.
14. K. K. Kim, Y.-B. Kim, M. Choi, and N. Park, "Leakage minimization technique for nanoscale CMOS VLSI based on macro-cell modeling," IEEE Des. Test. Comput., vol.24, no.4, pp. 322-330, Jul./ Aug. 2007.
15. S. G. Narendra and A. P. Chandrakasan, Leakage in Nanometer CMOS Technologies. Berlin, Germany: Springer-Verlag, 2006, pp. 21-40.
16. K. K. Kim and Y.-B. Kim, "A novel adaptive design methodology for minimum leakage power considering PVT variations on nanoscale VLSI systems," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.17, no.4, pp. 517-528, Apr. 2009.
17. H. Jeon, Y.-B. Kim, and M. Choi, "A novel technique to minimize standby leakage power in nanoscale CMOS VLSI," in Proc. I2MTC, Singapore, May 5-7, 2009, pp. 1372-1375.