An abstraction-aware compiler for VHDL models

Proceedings - The 2009 International Conference on Computer Engineering and Systems, ICCES'09

Volumn , Issue , 2009, Pages 3-9

  Maksoud, Mohamed Abdel ^a   Pister, Markus ^b   Schlickling, Marc ^b  

^a SAARLAND UNIVERSITY   (Germany)

^b AbsInt GmbH   (Germany)

Author keywords

Computer aided analysis; Hardware design languages; Real time systems; Software verification and validation; System analysis and design; Timing analysis

Indexed keywords

ABSTRACT INTERPRETATIONS; CONTROL SOFTWARE; ERROR-PRONE PROCESS; FLIGHT CONTROL COMPUTER; HARD REAL-TIME SYSTEMS; HARDWARE DESIGN LANGUAGE; HUMAN EXPERT; SAFETY-CRITICAL; SYSTEM ANALYSIS AND DESIGN; TIMING ANALYSIS; TIMING MODELS; UPPER BOUND; VHDL-MODEL; WORST-CASE EXECUTION TIME;

ABSTRACTING; AUTOMOTIVE INDUSTRY; COMPUTER AIDED ANALYSIS; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; COMPUTER SOFTWARE SELECTION AND EVALUATION; DESIGN; FLIGHT CONTROL SYSTEMS; HARDWARE; INTERACTIVE COMPUTER SYSTEMS; LINGUISTICS; PROGRAM COMPILERS; SYSTEMS ANALYSIS; TIME MEASUREMENT; VERIFICATION;

REAL TIME SYSTEMS;

EID: 77950448345     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCES.2009.5383321     Document Type: Conference Paper

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