Shallow and deep trench isolation for use in RF-Bipolar IC:s

European Solid-State Device Research Conference

Volumn , Issue , 2000, Pages 212-215

  Forsberg, M ^a   Bormander, C ^a   Johansson, T ^a   Ko, T ^b   Liu, W ^b   Vellaikal, M ^b   Cheshire, A ^c  

^a ERICSSON RESEARCH   (Sweden)

^b APPLIED MATERIALS INC   (United States)

^c Applied Materials UK Ltd   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

SOLID STATE DEVICES;

BI-CMOS; DEEP TRENCH ISOLATION; ELECTRICAL DATA; PLANARITY; PROCESS DATA; SELF-ALIGNED; SEM MICROGRAPHS;

SEMICONDUCTING SILICON;

EID: 77950313091     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2000.194752     Document Type: Conference Paper

References (3)

1. M. Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder, I.-C. Chen, "Shallow Trench Isolation for advanced ULSI CMOS Technologies", 1998 IEDM Tech. Dig., p. 133.
2. P. Hunt, M. P. Cooke "Process HE: a highly advanced trench isolated bipolar technology for analogue and digital applications", Proc. IEEE CICC 1988, p. 816.
3. R. D. Rung, H. Momose, Y. Nagakubo, "Deep trench isolated CMOS devices", 1982 IEDM Tech. Dig., p. 237.