Influence of gate misalignment on the electrical characteristics of MuGFETs

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2009, Pages 125-126

  Lee, Chi Woo ^a   Afzalian, Aryan ^a   Yan, Ran ^a   Dehdashti, Nima ^a   Xiong, Weize ^b   Colinge, Jean Pierre ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D SIMULATIONS; BREAKDOWN VOLTAGE; DEVICE CHARACTERISTICS; ELECTRICAL CHARACTERISTIC; ELECTRICAL PROPERTY; FIN WIDTHS; GATE CONTROL; GATE MISALIGNMENT; WORK STUDY;

ALIGNMENT; FINS (HEAT EXCHANGE); SECURITY SYSTEMS; THREE DIMENSIONAL COMPUTER GRAPHICS;

ELECTRIC PROPERTIES;

EID: 77950165789     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2009.5159322     Document Type: Conference Paper

References (4)

1. J.P. Colinge Solid-State Electron, vol.48, p.897, 2004.
2. T. Schulz et al. IEEE SOI Conference, p.154, 2005.
3. http://www.silvaco.com/
4. H.S Wong et al. Solid-State Electron vol.30, p.953, 1987.