A hierarchical methodology for word-length optimization of signal processing systems

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2010, Pages 318-323

  Parashar, Karthick ^a   Rocher, Romuald ^a   Menard, Daniel ^a   Sentieys, Olivier ^a  

^a INRIA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMIC LEVELS; DIVIDE AND CONQUER; DIVIDE-AND-CONQUER TECHNIQUE; ERROR PROPAGATION; FIXED POINTS; FLOATING-POINT ALGORITHMS; IMPLEMENTATION COST; MIXED APPROACH; NOISE SOURCE; OPTIMIZATION PROBLEMS; SIGNAL PROCESSING SYSTEMS; WORD LENGTH;

DESIGN; HIERARCHICAL SYSTEMS; SIGNAL PROCESSING;

EMBEDDED SYSTEMS;

EID: 77949996693     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2010.66     Document Type: Conference Paper

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