New approach to look-up-table design and memory-based realization of FIRk digital filter

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 3, 2010, Pages 592-603

  Meher, Pramod Kumar ^a  

^a INSTITUTE FOR INFOCOMM RESEARCH   (Singapore)

Author keywords

Digital signal processing (DSP) chip; Distributed arithmetic; FIR filter; LUT based computing; Memory based computing; VLSI

Indexed keywords

AREA EFFICIENT; COEFFICIENT VECTOR; DESIGN COMPILER; DIGITAL SIGNAL PROCESSING CHIPS; DISTRIBUTED ARITHMETIC; FILTER COEFFICIENTS; FILTER OUTPUT; FINITE IMPULSE RESPONSE FILTER; INNER PRODUCT; LOOK-UP-TABLE; MEMORY ELEMENT; MEMORY SIZE; NEW APPROACHES; NOR GATES; SYNOPSYS;

ADDERS; DECODING; DESIGN; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; FILTER BANKS; FREQUENCY MULTIPLYING CIRCUITS; IMPULSE RESPONSE; SIGNAL PROCESSING;

FIR FILTERS;

EID: 77949423990     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2026683     Document Type: Article

References (34)

1. J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principles, Algorithms and Applications. Upper Saddle River, NJ: Prentice- Hall, 1996.
2. G. Mirchandani, R. L. Zinser Jr., and J. B. Evans, "A new adaptive noise cancellation scheme in the presence of crosstalk [speech signals]," IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol.39, no.10, pp. 681-694, Oct. 1995.
3. D. Xu and J. Chiu, "Design of a high-order FIR digital filtering and variable gain ranging seismic data acquisition system," in Proc. IEEE Southeastcon'93, Apr. 1993, p. 6.
4. K. K. Parhi, VLSI Digital Signal Procesing Systems: Design and Implementation. New York: Wiley, 1999.
5. H. H. Kha, H. D. Tuan, B.-N. Vo, and T. Q. Nguyen, "Symmetric orthogonal complex-valued filter bank design by semidefinite programming," IEEE Trans. Signal Process., vol.55, no.9, pp. 4405-4414, Sep. 2007.
6. H. H. Dam, A. Cantoni, K. L. Teo, and S. Nordholm, "FIR variable digital filter with signed power-of-two coefficients," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.54, no.6, pp. 1348-1357, Jun. 2007.
7. R. Mahesh and A. P. Vinod, "A new common subexpression elimination algorithm for realizing low-complexity higher order digital filters," IEEE Trans. Computer-Aided Ded. Integr. Circuits Syst., vol.27, no.2, pp. 217-229, Feb. 2008.
8. International Technology Roadmap for Semiconductors, [Online]. Available: http://public.itrs.net/
9. B. Prince, "Trends in scaled and nanotechnology memories," in Proc. IEEE Conf. Custom Integr. Circuits, Nov. 2005, pp. 7
10. K. Itoh, S. Kimura, and T. Sakata, "VLSI memory technology: Current status and future trends," in Proc. 25th Eur. Solid-State Circuits Conference,{ ESSCIRC'99, Sep. 1999, pp. 3-10.
11. T. Furuyama, "Trends and challenges of large scale embedded memories," in Proc. IEEE Conf. Custom Integrated Circuits, Oct. 2004, pp. 449-456.
12. D. G. Elliott, M. Stumm, W. M. Snelgrove, C. Cojocaru, and R. Mckenzie, "Computational RAM: Implementing processors in memory," IEEE Trans. Design Test Comput., vol.16, no.1, pp. 32-41, Jan. 1999.
13. H.-R. Lee, C.-W. Jen, and C.-M. Liu, "On the design automation of the memory-based VLSI architectures for FIR filters," IEEE Trans. Consum. Electron., vol.39, no.3, pp. 619-629, Aug. 1993.
14. S. A. White, "Applications of the distributed arithmetic to digital signal processing:Atutorial review," IEEE ASSP Mag., vol.6, no.3, pp. 5-19, Jul. 1989.
15. M. Mehendale, S. D. Sherlekar, and G.Venkatesh, "Area-delay tradeoff in distributed arithmetic based implementation of FIR filters," in Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 124-129.
16. H. Yoo and D. V. Anderson, "Hardware-efficient distributed arithmetic architecture for high-order digital filters," in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing, (ICASSP'05), Mar. 2005, vol.5, pp. v/125-v/128.
17. D. J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. V. Anderson, "LMS adaptive filters using distributed arithmetic for high throughput," IEEE Trans. Circuits Systems I, Reg. Papers, vol.52, no.7, pp. 1327-1337, Jul. 2005.
18. S.-S. Jeng, H.-C. Lin, and S.-M. Chang, "FPGA implementation of FIR filter using M-bit parallel distributed arithmetic," in Proc. 2006 IEEE Intl. Symp. Circuits Syst. ISCAS 2006, May 2006, pp. 4
19. Y. H. Chan and W. C. Siu, "On the realization of discrete cosine transform using the distributed arithmetic," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.39, no.9, pp. 705-712, Sep. 1992.
20. H.-C. Chen, J.-I. Guo, T.-S. Chang, and C.-W. Jen, "A memory-efficient realization of cyclic convolution and its application to discrete cosine transform," IEEE Trans. Circuits Syst. Video Technol., vol.15, no.3, pp. 445-453, Mar. 2005.
21. M. Z. Zhang and V. K. Asari, "A fully pipelined multiplierless architecture for 2-D convolution with quadrant symmetric kernels," in Proc. IEEE Asia Pacific Conf. Circuits Syst., APCCAS 2006, Dec. 2006, pp. 1559-1562.
22. P. K. Meher, S. Chandrasekaran, and A. Amira, "FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic," IEEE Trans. Signal Process., vol.56, no.7, pp. 3009-3017, Jul. 2008.
23. P. K. Meher, "Unified systolic-like architecture forDCT and DST using distributed arithmetic," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.53, no.5, pp. 2656-2663, Dec. 2006.
24. J.-I. Guo, C.-M. Liu, and C.-W. Jen, "The efficient memory-based VLSI array design for DFT and DCT," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.39, no.10, pp. 723-733, Oct. 1992.
25. D. F. Chiper, "A systolic array algorithm for an efficient unified memory-based implementation of the inverse discrete cosine transform," in IEEE Conf. Image Process., Oct. 1999, pp. 764-768.
26. D. F. Chiper, M. N. S. Swamy, M. O. Ahmad, and T. Stouraitis, "Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.52, no.6, pp. 1125-1137, Jun. 2005.
27. P. K. Meher and M. N. S. Swamy, "New systolic algorithm and array architecture for prime-length discrete sine transform," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.54, no.3, pp. 262-266, Mar. 2007.
28. P. K. Meher, J. C. Patra, and M. N. S. Swamy, "High-throughput memory-based architecture for DHT using a new convolutional formulation," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.54, no.7, pp. 606-610, Jul. 2007.
29. J. P. Choi, S.-C. Shin, and J.-G. Chung, "Efficient ROM size reduction for distributed arithmetic," in Proc. IEEE Int. Symp. Circuits Syst. ISCAS, May 2000, vol.2, pp. 61-64.
30. P. K. Meher, "New approach to LUT implementation and accumulation for memory-based multiplication," in Proc. 2009 IEEE Int. Symp. Circuits Syst., ISCAS'09, May 2009, pp. 453-456.
31. A. K. Sharma, Advanced Semiconductor Memories : Architectures, Designs, and Applications. Piscataway, NJ: IEEE Press, 2003.
32. E. John, "Semiconductor memory circuits," in Digital Design and Fabrication, V. G. Oklobdzija, Ed. Boca Raton, FL: CRC Press, 2008.
33. Synposys, DesignWare. Foundry Libraries, Mountain View, CA, [Online]. Available: http://www.synopsys.com/
34. P. K. Meher, "New look-up-table optimizations for memory-based multiplication," in Proc. Int. Symp. Integr. Circuits (ISIC'09), Dec. 2009, to be published