An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher

Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09

Volumn , Issue , 2009, Pages 30-37

  Yao, Lifan ^a   Feng, Hao ^b   Zhu, Yiqun ^a   Jiang, Zhiguo ^b   Zhao, Danpei ^b   Feng, Wenquan ^b  

^a UNIVERSITY OF NOTTINGHAM   (United Kingdom)

^b BEIHANG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DOWNSAMPLING; FEATURE DESCRIPTORS; FEATURE DETECTION; FPGA IMPLEMENTATIONS; HARDWARE RESOURCES; MATCHING PERFORMANCE; OPTIMISATIONS; PROPOSED ARCHITECTURES; SCALE INVARIANT FEATURE TRANSFORMS; SIFT FEATURE; UPSAMPLING;

IMAGE MATCHING; PIXELS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77949422486     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2009.5377651     Document Type: Conference Paper

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