Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 3, 2010, Pages 681-690

  Cao, Zhen ^a   Foo, Brian ^b   He, Lei ^a   Van Der Schaar, Mihaela ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b LOCKHEED MARTIN SPACE SYSTEMS COMPANY   (United States)

Author keywords

Dynamic voltage scaling (DVS); Energy management; Linear programming (LP); Multimedia communication; Scheduling; System modeling

Indexed keywords

ENERGY MANAGEMENT; ENERGY UTILIZATION; LINEAR PROGRAMMING; SCHEDULING; VOLTAGE SCALING;

DYNAMIC VOLTAGE SCALING (DVS); MINIMUM ENERGY CONSUMPTION; MULTI-MEDIA COMMUNICATIONS; MULTIMEDIA APPLICATIONS; OPTIMAL LOWER BOUND; REAL-TIME APPLICATION; SEQUENTIAL LINEAR PROGRAMMING; SYSTEM MODELING;

MULTIMEDIA SYSTEMS;

EID: 77949409696     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2023941     Document Type: Article

References (34)

1. L. Benini and G. De Micheli, Dynamic Power Management: Design Techniques and CAD Tools. Norwell, MA: Kluwer, 1997.
2. D. Marculescu, "On the use of microarchitecture-driven dynamic voltage scaling," in Proc. Workshop Complexity Eff. Des., 2000.
3. J. Lorch and A. Smith, "PACE: A new approach to dynamic voltage scaling," IEEE Trans. Comput., vol.53, no.7, pp. 856-869, Jul. 2004.
4. T. Ishihara and H. Yasuura, "Voltage scheduling problem for dynamically variable voltage processors," presented at the presented at the Int. Symp. Low-Power Electron. Design, Monterey, CA, 1998.
5. P. Pillai and K. Shin, "Real-time dynamic voltage scaling for lowpower embedded operating systems," in Proc. 18th ACM Symp. Oper. Syst., 2001, pp. 89-102.
6. W. Yuan, K. Nahrstedt, S. Adve, and D. J. Kravets, "GRACE: Cross-layer adaptation for multimedia quality and battery energy," IEEE Trans. Mobile Comput., vol.5, no.7, pp. 799-815, Jul. 2006.
7. W.Yuan and K. Nahrstedt, "Energy-efficient soft real-time CPU scheduling for mobile multimedia systems," in Proc. 19th ACM Symp. Oper. Syst. Principles, 2003, pp. 149-163.
8. Y. Zhu and F. Mueller, "Feedback EDF scheduling exploiting dynamic voltage scaling," in Proc. 11th Int. Conf. Comput. Arch., 2004, pp. 84-93.
9. K. Choi, K. Dantu, W. Cheng, and M. Pedram, "Frame-based dynamic voltage and frequency scaling for a MPEG decoder," in Proc. ICCAD, 2002, pp. 732-737.
10. Y. Zhu and F. Mueller, "DVSleak: Combining leakage reduction and voltage scaling in feedback EDF scheduling," in Proc. LCTES, 2007, pp. 31-40.
11. A. Maxiaguine, S. Chakraborty, and L. Thiele, "DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs," in Proc. 3rd IEEE/ACM/IFIP Int. Conf. Hardware/Softw. Codes. Syst. Synth., 2005, pp. 111-116.
12. E. Akyol and M. Van Der Schaar, "Complexity model based proactive dynamic voltage scaling for video decoding systems," IEEE Trans. Multimedia, vol.9, no.7, pp. 1475-1492, Nov. 2007.
13. B. Foo and M. Van Der Schaar, "A queuing theoretic approach to processor power adaptation for video decoding systems," IEEE Trans. Signal Process, vol.56, no.1, pp. 378-392, Jan. 2008.
14. H. Aydin, R. Melhem, D. Mosse, and P. Mejia-Alvarez, "Power-aware scheduling for periodic real-time tasks," IEEE Trans. Comput., vol.53, no.5, pp. 584-600, May 2004.
15. C. Xian, Y.-H. Lu, and Z. Li, "Dynamic voltage scaling for multitasking real-time systems with uncertain execution time," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.27, no.8, pp. 1467-1478, Aug. 2008.
16. R. Jejurikar, C. Pereira, and R. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems," in Proc. DAC, 2004, pp. 275-280.
17. S. Martin, K. Flautner, T.Mudge, and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for low power microprocessors under dynamic workloads," in Proc. ICCAD, 2002, pp. 721-725.
18. C. Kim and K. Roy, "Dynamic VTH scaling scheme for active leakage power reduction," in Proc. Des., Autom., Test Eur., 2002, pp. 163-167.
19. L. Yan, J. Luo, and N. K. Jha, "Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.24, no.7, pp. 1030-1041, Jul. 2005.
20. S. Hong, S. Yoo, B. Bin, K.-M. Choi, S.-K. Eo, and T. Kim, "Dynamic voltage scaling of supply and body bias exploiting software runtime distribution," in Proc. Des., Autom., Test Eur., 2008, pp. 242-247.
21. S. Zhang and K. S. Chatha, "Approximation algorithm for the temperature- aware scheduling problem," in Proc. ICCAD, 2007, pp. 281-288.
22. R. Jayaseelan and T. Mitra, "Temperature aware task sequencing and voltage scaling," in Proc. ICCAD, 2008, pp. 618-623.
23. S. Zhang and K. Chatha, "System-level thermal aware design of applications with uncertain execution time," in Proc. ICCAD, 2008, pp. 242-249.
24. J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors," IEEE J. Solid-State Circuits, vol.30, no.4, pp. 412-422, Apr. 1995.
25. A. Adas, "Traffic models in broadband networks," IEEE Commun. Mag., vol.35, no.7, pp. 82-89, Jul. 1997.
26. M. Van Der Schaar and Y. Andreopoulos, "Rate-distortion-complexity modeling for network and receiver aware adaptation," IEEE Trans. Multimedia, vol.7, no.3, pp. 471-479, Jun. 2005.
27. Z. Cao, B. Foo, L. He, and M. Van Der Schaar, "Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications," in Proc. DAC, 2008, pp. 179-184.
28. J. Pouwelse, K. Langendoen, and H. Sips, "Application-directed voltage scaling," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.11, no.5, pp. 812-826, Oct. 2003.
29. D. Biermann, E. G. Sirer, and R. Manohar, "A rate matching-based approach to dynamic voltage scaling," in Proc. 1st Watson Conf. Interact. Between Arch., Circuits, Compilers, Oct. 2004, pp. 1-10.
30. A. Schrijver, Theory of Linear and Integer Programming. New York: Wiley, 1986.
31. S. Boyd and L. Vandenberghe, Convex Optimization. Cambridge, U.K.: Cambridge Univ. Press, 2003.
32. Y. Cho and N. Chang, "Energy-aware clock-frequency assignment in microprocessors and memory devices for dynamic voltage scaling," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.26, no.6, pp. 1030-1040, Jun. 2007.
33. D. Ma, "Automatic substrate switching circuit for on-chip adaptive power-supply system," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.54, no.7, pp. 641-645, Jul. 2007.
34. X. Zhong and C. Xu, "System-wide energy minimization for real-time tasks: Lower bound and approximation," in Proc. ICCAD, 2006, pp. 516-521.