Optimal buck converter output filter design for point-of-load applications

IEEE Transactions on Industrial Electronics

Volumn 57, Issue 4, 2010, Pages 1330-1341

  De Nardo, Antonietta ^a   Femia, Nicola ^a   Petrone, Giovanni ^a   Spagnuolo, Giovanni ^a  

^a UNIVERSITY OF SALERNO   (Italy)

Author keywords

DC DC converter design; Point of load (POL); Power supplies; Voltage regulator module

Indexed keywords

ANALYTICAL RESULTS; BOUNDARY CURVES; BUCK CONVERTERS; COMMERCIAL COMPONENTS; DESIGN METHOD; DESIGN SPECIFICATION; EXPERIMENTAL MEASUREMENTS; FUNCTIONAL CORRELATION; NOVEL METHODS; NUMERICAL PREDICTIONS; OUTPUT FILTERS; OUTPUT VOLTAGE RIPPLE; POINT OF LOADS; POWER COMPONENTS; POWER SUPPLY; SWITCHING REGULATOR; TRADE-OFF DESIGN; TRANSIENT SURGE; VOLTAGE REGULATOR MODULE;

DC-DC CONVERTERS; ELECTRIC CONVERTERS; ELECTRIC LOADS; ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; VOLTAGE CONTROL; VOLTAGE REGULATORS;

DESIGN;

EID: 77949405679     PISSN: 02780046     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIE.2009.2030219     Document Type: Article

References (16)

1. J. F. Da Rocha, M. B. Dos Santos, J. M. Dores Costa, and F. A. Lima, "Level shifters and DCVSL for a low-voltage CMOS 4.2-V buck converter," IEEE Trans. Ind. Electron., vol.55, no.9, pp. 3315-3323, Sep. 2008.
2. M. Castilla, L. G. De Vicuna, J. M. Guerrero, J. Matas, and J. Miret, "Designing VRM hysteretic controllers for optimal transient response," IEEE Trans. Ind. Electron., vol.54, no.3, pp. 1726-1738, Jun. 2007.
3. A. Simon-Muela, S. Petibon, C. Alonso, and J.-L. Chaptal, "Practical implementation of a high-frequency current-sense technique for VRM," IEEE Trans. Ind. Electron., vol.55, no.9, pp. 3221-3230, Sep. 2008.
4. E. Dallago, M. Passoni, and G. Sassone, "Lossless current sensing in low voltage high current DC/DC modular supplies," IEEE Trans. Ind. Electron., vol.47, no.6, pp. 1249-1252, Dec. 2000.
5. J.-J. Lee and B.-H. Kwon, "DC-DC converter using a multiple-coupled inductor for low output voltages," IEEE Trans. Ind. Electron., vol.54, no.1, pp. 467-478, Feb. 2007.
6. Y. Panov and M. M. Jovanovic, "Design considerations for 12-V/1.5-V, 50-A voltage regulator modules," IEEE Trans. Power Electron., vol.16, no.6, pp. 776-783, Nov. 2001.
7. A. Barrado, A. Lazaro, R. Vazquez, V. Salas, and E. Olias, "The fast response double buck DC-DC converter (FRDB): Operation and output filter influence," IEEE Trans. Power Electron., vol.20, no.6, pp. 1261- 1270, Nov. 2005.
8. K. Yao, Y. Ren, and F. C. Lee, "Critical bandwidth for load transient response of voltage regulator modules," IEEE Trans. Power Electron., vol.19, no.6, pp. 1454-1461, Nov. 2004.
9. D. D. C. Lu, J. C. P. Liu, F. N. K. Poon, and B. M. H. Pong, "A single phase voltage regulator module (VRM) with stepping inductance for fast transient response," IEEE Trans. Power Electron., vol.22, no.2, pp. 417- 424, Mar. 2007.
10. S. K. Changchien, T. J. Liang, J. F. Chen, and L. S. Yang, "Fast response DC/DC converter with transient suppression circuit," in Proc. IEEE PESC, Jun. 2006, pp. 1-5.
11. T. Senanayake and T. Ninomiya, "An improved topology of inductorswitching DC-DC converter," IEEE Trans. Ind. Electron., vol.52, no.3, pp. 869-878, Jun. 2005.
12. A. Consoli, A. Testa, G. Giannetto, and F. Gennaro, "A new VRM topology for next generation microprocessors," in Proc. IEEE PESC, Jun. 2001, vol.1, pp. 339-344.
13. E. Meyer and Y.-F. Liu, "A quick capacitor charge balance control method to achieve optimal dynamic response for buck converters," in Proc. IEEE PESC, Jun. 17-21, 2007, pp. 1549-1555.
14. H. Peng and D.Maksimovic, "Digital current mode controller for DC-DC converters," in Proc. IEEE APEC, 2005, vol.2, pp. 899-905.
15. G. Feng, E. Meyer, and Y.-F. Liu, "A new digital control algorithm to achieve optimal dynamic performance in DC-to-DC converters," IEEE Trans. Power Electron., vol.22, no.4, pp. 1489-1498, Jul. 2007.
16. P. L. Wong, F. C. Lee, P. Xu, and K. Yao, "Critical inductance in voltage regulator modules," IEEE Trans. Power Electron., vol.17, no.4, pp. 485- 492, Jul. 2002.