Bounded sequence testing from deterministic finite state machines

Theoretical Computer Science

Volumn 411, Issue 16-18, 2010, Pages 1770-1784

  Ipate, Florentin ^a  

^a UNIVERSITY OF PITESTI   (Romania)

Author keywords

Finite state machines; Specification based testing; Test selection; W p method; W method

Indexed keywords

CONFORMANCE TESTING; FINITE STATE MACHINES; IMPLEMENTATION UNDER TESTS; INPUT SEQUENCE; SPECIFICATION BASED TESTING; TEST DATA; TEST GENERATION ALGORITHM; TEST SELECTION; TEST SEQUENCE; UPPER BOUND;

CONTOUR FOLLOWERS; FINITE AUTOMATA; SPECIFICATIONS;

TESTING;

EID: 77949261557     PISSN: 03043975     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.tcs.2010.01.030     Document Type: Article

References (32)

1. Bǎlǎnescu T., Gheorghe M., Ipate F., and Holcombe M. Formal black box testing for partially specified deterministic finite state machines. Foundations of Computing and Decision Systems 28 1 (2003) 17-28
2. Bǎlǎnescu T., and Ipate F. The Wp method for partially specified deterministic finite state machines. Annals of Bucharest University: Computer Science LIII 1 (2004) 47-60
3. A. Biere, A. Cimatti, E.M. Clarke, Y. Zhu, Symbolic Model Checking without BDDs, in: Proceedings of Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS, 1999, pp. 193-207.
4. Campeanu C., Santean N., and Yu S. Minimal cover automata for finite languages. Theoretical Computer Science 267 (1999) 3-16
5. Chow T.S. Testing software design modeled by finite state machines. IEEE Transactions on Software Engineering 4 3 (1978) 178-187
6. Eilenberg S. Automata, languages and machines vol. A. (1994), Academic Press, New York
7. En-Nouaary A., Dssouli R., and Khendek F. Timed Wp-method: Testing real-time systems. IEEE Transactions on Software Engineering 28 11 (2002) 1023-1038
8. T. Filkorn, A method for symbolic verification of synchronous circuits, in: Proc. Int. Symp. Comput. Hardware Description Lang. Applicat., 1991, pp. 249-259.
9. Fujiwara S., von Bochmann G., Khendek F., Amalou M., and Ghedamsi A. Test selection based on finite state models. IEEE Transactions on Software Engineering 17 6 (1991) 591-603
10. Gill A. Introduction to the Theory of Finite-State Machines (1962), McGraw-Hill
11. Harel D., and Politi M. Modeling Reactive Systems with Statecharts: the STATEMATE Approach (1998), McGraw-Hill, New York
12. Hierons R.M. Testing from a non-deterministic finite state machine using adaptive state counting. IEEE Transactions on Computers 53 10 (2004) 1330-1342
13. Holcombe M., and Ipate F. Correct Systems: Building a Business Process Solution (1998), Springer Verlag, Berlin
14. Hopcroft J.E., and Ullman J.D. Introduction to Automata Theory, Languages and Computation. (1979), Addison Wesley, Reading, MA
15. Ipate F. On the minimality of finite automata and stream x-machines for finite languages. The Computer Journal 48 2 (2005) 157-167
16. Ipate F., and Holcombe M. An integration testing method that is proved to find all faults. International Journal of Computer Mathematics 63 (1997) 159-178
17. Ipate F. Complete deterministic stream X-machine testing. Formal Aspects of Computing 16 4 (2004) 374-386
18. Ipate F. Testing against a non-controllable stream X-machine using state counting. Theoretical Computer Science 353 1-3 (2006) 291-316
19. ITU-T. Recommendation Z.100 Specification and description language (SDL). International Telecommunications Union, Geneva, Switzerland, 1999.
20. Jiang J.-H.R., and Brayton R.K. On the verification of sequential equivalence. International Workshop on Logic and Synthesis, (IWLS) 22 6 (2002) 307-314
21. Korner H. On minimizing cover automata for finite languages in O(n log n) time. LNCS 2608 (2003) 117-127
22. Lee D., and Yannakakis M. Principles and methods of testing finite state machines - a survey. Proceedings of the IEEE 84 8 (1996) 1090-1123
23. Miczo A. Digital Logic Testing and Simulation. 2nd ed. (2003), John Wiley & Sons
24. 2) algorithm for constructing minimal cover automata for finite languages. Lecture Notes in Computer Science vol. 2088 (2001), Springer 243-251
25. A. Petrenko, N. Yevtushenko, G. von Bochmann, Testing deterministic implementations from nondeterministic FSM specifications, in: Proc. of 9th International Workshop on Testing of Communicating Systems, IWTCS'96, 1996, pp. 125-140.
26. Petrenko A., and Yevtushenko N. Testing from partial deterministic FSM specifications. IEEE Transactions on Computers 54 9 (2005) 1154-1165
27. Prasad M.K., Biere A., and Gupta A. A survey of recent advances in SAT-based formal verification. Software Tools for Technology Transfer, (STTT) 7 2 (2005) 156-173
28. Ramalingam T., Das A., and Thulasiram K. Fault detection and diagnosis capabilities of test sequence selection methods based on the fsm model. Computer Communications 18 2 (1995) 113-122
29. Ramalingam T., Das A., and Thulasiram K. On testing and diagnosis of communication protocols based on the fsm model. Computer communications 18 5 (1995) 329-337
30. Shen Y.-N., Lombardi F., and Dahbura A.T. Protocol conformance testing using multiple uio sequences. In: Brinksma E., Scollo G., and Vissers C.A. (Eds). Protocol Specification, Testing and Verification IX (1990), Elsevier Schene Publishers B.V, North-Holland 131-143
31. Sidhu D., and Leung T. Formal methods for protocol testing: A detailed study. IEEE Transactions on Software Engineering 15 4 (1989) 413-426
32. Ural H. Formal methods for test sequence generation. Computer Communications 15 5 (1992) 311-325