The design of co-processor for the image processing single chip system

ICCIT 2009 - 4th International Conference on Computer Sciences and Convergence Information Technology

Volumn , Issue , 2009, Pages 943-946

  Wu, Liming ^a   Liu, Junxiu ^a   Luo, Yuling ^a  

^a GUANGDONG UNIVERSITY OF TECHNOLOGY   (China)

Author keywords

Bitonic sort; Embedded system; Image processing; Parallel computing

Indexed keywords

BITONIC SORT; CO-PROCESSORS; CORE PROCESSORS; EMBEDDED DESIGNS; FAST IMAGE PROCESSING; HARDWARE/SOFTWARE; MEDIAN FILTER; ON CHIP MEMORY; PARALLEL COMPUTING; PROCESS SPEED; SINGLE CHIPS; SOFT-CORE PROCESSORS; SYSTEM ARCHITECTURES; SYSTEM ON A PROGRAMMABLE CHIPS;

COMPUTER SCIENCE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; IMAGING SYSTEMS; INFORMATION TECHNOLOGY; PARALLEL ARCHITECTURES;

MILITARY PHOTOGRAPHY;

EID: 77749317349     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCIT.2009.26     Document Type: Conference Paper

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