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Volumn , Issue , 2009, Pages

An ILP formulation for application mapping onto Network-on-Chips

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION MAPPING; BUS-BASED; COMMUNICATION METHOD; COMPUTATION TIME; ENERGY CONSUMPTION; ILP FORMULATION; INTEGER LINEAR PROGRAMMING; MESH ARCHITECTURE; NETWORK ON CHIP; NETWORK-ON-CHIPS; OPTIMAL RESULTS; SIGNAL INTEGRITY; SIGNAL PROPAGATION DELAYS; SYSTEM-ON-CHIP ARCHITECTURE;

EID: 77749309823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICAICT.2009.5372524     Document Type: Conference Paper
Times cited : (73)

References (12)
  • 1
    • 77749237260 scopus 로고    scopus 로고
    • Visit http://www.itrs.net for ITRS 2007 edition.
    • Visit
  • 2
    • 0034848112 scopus 로고    scopus 로고
    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • Las Vegas, Nevada, USA, pp
    • W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. Design Automation Conference, Las Vegas, Nevada, USA, pp. 684-689, 2001.
    • (2001) Proc. Design Automation Conference , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 3
    • 0036149420 scopus 로고    scopus 로고
    • Networks on Chips: A New SoC Paradigm
    • Jan
    • L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
    • (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 4
    • 77749240229 scopus 로고    scopus 로고
    • Visit http://techresearch.intel.com/articles/Tera-Scale/1421.html for Tera-Scale Computing Research Program.
    • Visit http://techresearch.intel.com/articles/Tera-Scale/1421.html for Tera-Scale Computing Research Program.
  • 6
    • 3042567207 scopus 로고    scopus 로고
    • Bandwidth-Constrained Mapping of Cores onto NoC Architectures
    • Feb, Paris, France
    • S. Murali and G. De Micheli, "Bandwidth-Constrained Mapping of Cores onto NoC Architectures," Proc. DATE'04, vol.2, pp. 896-304, Feb. 2004, Paris, France.
    • (2004) Proc. DATE'04 , vol.2 , pp. 896-304
    • Murali, S.1    De Micheli, G.2
  • 7
    • 28444439962 scopus 로고    scopus 로고
    • A technique for low energy mapping and routing in network-on-chip architectures
    • Aug, San Diego, California
    • K. Srinivasan and K. S. Chatha, "A technique for low energy mapping and routing in network-on-chip architectures," Proc. ISLPED'05, pp. 387-392, Aug. 2005, San Diego, California.
    • (2005) Proc. ISLPED'05 , pp. 387-392
    • Srinivasan, K.1    Chatha, K.S.2
  • 8
    • 58849135725 scopus 로고    scopus 로고
    • Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip
    • Jan
    • M. Janidarmian, A. Khademzadeh, and M. Tavanpour, "Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip," IEICE Electron. Express, vol. 6, no. 1, pp. 1-7, Jan., 2009.
    • (2009) IEICE Electron. Express , vol.6 , Issue.1 , pp. 1-7
    • Janidarmian, M.1    Khademzadeh, A.2    Tavanpour, M.3
  • 9
    • 58849097536 scopus 로고    scopus 로고
    • CGMAP: A new approach to Network-on-Chip mapping problem
    • Jan
    • F. Moein-darbari, A. Khademzade, and G. Gharooni-fard, "CGMAP: a new approach to Network-on-Chip mapping problem," IEICE Electron. Express, vol. 6, no. 1, pp. 27-34, Jan., 2009.
    • (2009) IEICE Electron. Express , vol.6 , Issue.1 , pp. 27-34
    • Moein-darbari, F.1    Khademzade, A.2    Gharooni-fard, G.3
  • 10
    • 77749234213 scopus 로고    scopus 로고
    • Visit http://www.dashoptimization.com for Xpress-MP.
    • Visit http://www.dashoptimization.com for Xpress-MP.
  • 11
    • 33746590812 scopus 로고    scopus 로고
    • Linear-programming-based techniques for synthesis of network-on-chip architectures
    • Apr
    • Srinivasan, K., Chatha, K. S., and Konjevod, G. 2006. Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. Very Large Scale Integr. Syst. 14, 4 (Apr. 2006), 407-420.
    • (2006) IEEE Trans. Very Large Scale Integr. Syst , vol.14 , Issue.4 , pp. 407-420
    • Srinivasan, K.1    Chatha, K.S.2    Konjevod, G.3
  • 12
    • 46649092517 scopus 로고    scopus 로고
    • Low-power algorithm for automatic topology generation for application-specific networks on chips
    • K.-C. Chang and T.-F. Chen, Low-power algorithm for automatic topology generation for application-specific networks on chips, IET Comput. Digit. Tech., 2008, Vol. 2, No. 3, pp. 239-249.
    • (2008) IET Comput. Digit. Tech , vol.2 , Issue.3 , pp. 239-249
    • Chang, K.-C.1    Chen, T.-F.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.