A symbolic verifier for CUDA programs

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Volumn , Issue , 2010, Pages 357-358

  Li, Guodong ^a   Gopalakrishnan, Ganesh ^a   Kirby, Robert M ^a   Quinlan, Dan ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

Author keywords

CUDA; Formal verification; SPMD; Symbolic analysis

Indexed keywords

DECISION PROCEDURE; FORMAL VERIFICATIONS; PARTIAL ORDER REDUCTIONS; RACE CONDITION; SYMBOLIC ANALYSIS; VERIFIER-BASED;

PROGRAM DEBUGGING;

PARALLEL PROGRAMMING;

EID: 77749243431     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1693453.1693512     Document Type: Conference Paper

References (7)

1. M. Boyer, K. Skadron and W.Weimer. Automated Dynamic Analysis of CUDA Programs. http://www.cs.virginia.edu/~mwb7w/cuda/.
2. CUDA Zone. http://www.nvidia.com/object/cuda-home.html.
3. Yices: An SMT Solver. http://yices.csl.sri.com.
4. The ROSE Compiler. http://www.rosecompiler.org/.
5. R. Lublinerman and S. Tripakis, Checking Equivalence of SPMD Programs Using Non-Interference. http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS- 2009-42.html.
6. Bounded Model Checking for ANSI-C. http://www.cprover.org/cbmc/.
7. I. Rabinovitz and O. Grumberg. Bounded Model Checking of Concurrent Programs. CAV, pp. 82-97, 2005.