-
1
-
-
45749123479
-
A unified-RAM (URAM) cell for multi-functioning capacitorless DRAM and NVM
-
J.-W. Han, S.-W. Ryu, C. Kim, S. Kim, M. Im, S. J. Choi, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, "A unified-RAM (URAM) cell for multi-functioning capacitorless DRAM and NVM," in IEDM Tech. Dig., 2007, pp. 929-932.
-
(2007)
IEDM Tech. Dig
, pp. 929-932
-
-
Han, J.-W.1
Ryu, S.-W.2
Kim, C.3
Kim, S.4
Im, M.5
Choi, S.J.6
Kim, J.S.7
Kim, K.H.8
Lee, G.S.9
Oh, J.S.10
Song, M.H.11
Park, Y.C.12
Kim, J.W.13
Choi, Y.-K.14
-
2
-
-
51949086339
-
Band offset FinFET-based URAM (Unified-RAM) built on SiC for multi-functioning NVM and capacitorless 1T-DRAM
-
J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, "Band offset FinFET-based URAM (Unified-RAM) built on SiC for multi-functioning NVM and capacitorless 1T-DRAM," in VLSI Symp. Tech. Dig., 2008, pp. 200-201.
-
(2008)
VLSI Symp. Tech. Dig
, pp. 200-201
-
-
Han, J.-W.1
Ryu, S.-W.2
Kim, S.3
Kim, C.-J.4
Ahn, J.-H.5
Choi, S.-J.6
Choi, K.J.7
Cho, B.J.8
Kim, J.S.9
Kim, K.H.10
Lee, G.S.11
Oh, J.S.12
Song, M.H.13
Park, Y.C.14
Kim, J.W.15
Choi, Y.-K.16
-
3
-
-
64549145387
-
Energy band engineered unified-RAM (URAM) for multi-functioning 1T-DRAM and NVM
-
J.-W. Han, S.-W. Ryu, S. Kim, C.-J. Kim, J.-H. Ahn, S.-J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, "Energy band engineered unified-RAM (URAM) for multi-functioning 1T-DRAM and NVM," in IEDM Tech. Dig., 2008, pp. 227-230.
-
(2008)
IEDM Tech. Dig
, pp. 227-230
-
-
Han, J.-W.1
Ryu, S.-W.2
Kim, S.3
Kim, C.-J.4
Ahn, J.-H.5
Choi, S.-J.6
Choi, K.J.7
Cho, B.J.8
Kim, J.S.9
Kim, K.H.10
Lee, G.S.11
Oh, J.S.12
Song, M.H.13
Park, Y.C.14
Kim, J.W.15
Choi, Y.-K.16
-
4
-
-
21644447069
-
Silicon on thin BOX: A new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control
-
R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, "Silicon on thin BOX: A new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control," in IEDM Tech. Dig., 2004, pp. 631-634.
-
(2004)
IEDM Tech. Dig
, pp. 631-634
-
-
Tsuchiya, R.1
Horiuchi, M.2
Kimura, S.3
Yamaoka, M.4
Kawahara, T.5
Maegawa, S.6
Ipposhi, T.7
Ohji, Y.8
Matsuoka, H.9
-
5
-
-
0034453365
-
Three-dimensional shared memory fabricated using wafer stacking technology
-
K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, and M. Koyanagi, "Three-dimensional shared memory fabricated using wafer stacking technology," in IEDM Tech. Dig., 2000, pp. 165-168.
-
(2000)
IEDM Tech. Dig
, pp. 165-168
-
-
Lee, K.W.1
Nakamura, T.2
Ono, T.3
Yamada, Y.4
Mizukusa, T.5
Hashimoto, H.6
Park, K.T.7
Kurino, H.8
Koyanagi, M.9
-
6
-
-
46049113542
-
Three dimensionally stacked NAND Flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30 nm node
-
S.-M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son, J. Park, M.-S. Song, K.-H. Kim, J.-S. Lim, and K. Kim, "Three dimensionally stacked NAND Flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30 nm node," in IEDM Tech. Dig., 2006, pp. 37-40.
-
(2006)
IEDM Tech. Dig
, pp. 37-40
-
-
Jung, S.-M.1
Jang, J.2
Cho, W.3
Cho, H.4
Jeong, J.5
Chang, Y.6
Kim, J.7
Rah, Y.8
Son, Y.9
Park, J.10
Song, M.-S.11
Kim, K.-H.12
Lim, J.-S.13
Kim, K.14
-
7
-
-
39749141707
-
Scalable 3-D finlike poly-Si TFT and its nonvolatile memory application
-
Feb
-
H. Yin, W. Xianyu, A. Tikhonovsky, and Y. S. Park, "Scalable 3-D finlike poly-Si TFT and its nonvolatile memory application," IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 578-584, Feb. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.2
, pp. 578-584
-
-
Yin, H.1
Xianyu, W.2
Tikhonovsky, A.3
Park, Y.S.4
-
8
-
-
59649117424
-
Gate-induced drainleakage (GIDL) programming method for soft-programming-free operation in unified RAM (URAM)
-
Feb
-
J.-W. Han, S.-W. Ryu, S.-J. Choi, and Y.-K. Choi, "Gate-induced drainleakage (GIDL) programming method for soft-programming-free operation in unified RAM (URAM)," IEEE Electron Device Lett., vol. 30, no. 2, pp. 189-191, Feb. 2009.
-
(2009)
IEEE Electron Device Lett
, vol.30
, Issue.2
, pp. 189-191
-
-
Han, J.-W.1
Ryu, S.-W.2
Choi, S.-J.3
Choi, Y.-K.4
-
9
-
-
0036494144
-
A spacer patterning technology for nanoscale CMOS
-
Mar
-
Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436-441, Mar. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.3
, pp. 436-441
-
-
Choi, Y.-K.1
King, T.-J.2
Hu, C.3
-
10
-
-
26244446788
-
Demonstration, analysis, and device design considerations for independent DG MOSFETs
-
Sep
-
M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, and E. Suzuki, "Demonstration, analysis, and device design considerations for independent DG MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2046-2053, Sep. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.9
, pp. 2046-2053
-
-
Masahara, M.1
Liu, Y.2
Sakamoto, K.3
Endo, K.4
Matsukawa, T.5
Ishii, K.6
Sekigawa, T.7
Yamauchi, H.8
Tanoue, H.9
Kanemaru, S.10
Koike, H.11
Suzuki, E.12
-
11
-
-
77649193606
-
High-performance thin-film transistors in large grain size polysilicon deposited by thermal decomposition of disilane
-
Sep
-
D. N. Kouvatsos, A. T. Voutsas, and M. K. Hatalis, "High-performance thin-film transistors in large grain size polysilicon deposited by thermal decomposition of disilane," IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 2046-2053, Sep. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.9
, pp. 2046-2053
-
-
Kouvatsos, D.N.1
Voutsas, A.T.2
Hatalis, M.K.3
-
12
-
-
0033342070
-
Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization
-
S. Jagar, M. Chan, M. C. Poon, H. Wang, M. Qin, P. K. Ko, and Y. Wang, "Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization," in IEDM Tech. Dig., 1999, pp. 293-296.
-
(1999)
IEDM Tech. Dig
, pp. 293-296
-
-
Jagar, S.1
Chan, M.2
Poon, M.C.3
Wang, H.4
Qin, M.5
Ko, P.K.6
Wang, Y.7
-
13
-
-
0025955121
-
Poly silicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film
-
Jan
-
N. Yamauchi, J.-J. J. Hajjar, and R. Reif, "Poly silicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film," IEEE Trans. Electron Devices, vol. 38, no. 1, pp. 55-60, Jan. 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, Issue.1
, pp. 55-60
-
-
Yamauchi, N.1
Hajjar, J.-J.J.2
Reif, R.3
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