Verification of real-time systems design

Software Testing Verification and Reliability

Volumn 20, Issue 1, 2010, Pages 3-37

  Cambronero, M Emilia ^a   Valero, Valentín ^a   Díaz, Gregorio ^a  

^a UNIVERSITY OF CASTILLA LA MANCHA   (Spain)

Author keywords

Design; Model checking; Real time systems; RT UML sequence diagrams; Timed automata; UPPAAL; Verification; XSLT

Indexed keywords

DESIGN MODELS; DESIGN PHASE; DESIGN PHASIS; MODEL-CHECKING TECHNIQUES; OBJECT MANAGEMENT GROUPS; REAL-TIME DYNAMICS; RT-UML SEQUENCE DIAGRAMS; SCHEDULABILITY; SYSTEM VERIFICATIONS; TIMED AUTOMATA; UML PROFILES; UML SEQUENCE DIAGRAMS; VALIDATION AND VERIFICATION;

AUTOMATA THEORY; DESIGN; DYNAMICAL SYSTEMS; GRAPHIC METHODS; MODEL CHECKING; ROBOTS; TIME MEASUREMENT; TRANSLATION (LANGUAGES);

REAL TIME SYSTEMS;

EID: 77449093958     PISSN: 09600833     EISSN: 10991689     Source Type: Journal    
DOI: 10.1002/stvr.405     Document Type: Article

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