Sequential verification of serializability

ACM SIGPLAN Notices

Volumn 45, Issue 1, 2010, Pages 31-42

  Attiya, H ^a   Ramalingam, G ^b   Rinetzky, N ^c  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^b MICROSOFT RESEARCH INDIA   (India)

^c QUEEN MARY UNIVERSITY OF LONDON   (United Kingdom)

Author keywords

Concurrency; Modular Analysis; Reduction; Serializability; Verification

Indexed keywords

COMPUTER PROGRAMMING; FORESTRY; REDUCTION; VERIFICATION;

CONCURRENCY; CONCURRENT PROGRAMMING; CORRECTNESS CONDITIONS; LOCKING PROTOCOLS; MODULAR ANALYSIS; SEQUENTIAL EXECUTION; SERIALIZABILITY; TWO-PHASE LOCKING;

LOCKS (FASTENERS);

EID: 77149168494     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1707801.1706305     Document Type: Conference Paper

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