Double-fin FETs based on standard CMOS approach

Microelectronic Engineering

Volumn 87, Issue 5-8, 2010, Pages 1396-1399

  Zaborowski, Michał ^a   Tomaszewski, Daniel ^a   Panas, Andrzej ^a   Grabiec, Piotr ^a  

^a ukasiewicz Research Network Institute of Microelectronics and Photonics   (Poland)

Author keywords

FinFETs; Nanoengineering; PaDEOx; Si nanolines

Indexed keywords

DEVICE PARAMETERS; FINFETS; NANO-ENGINEERING; NANOLINES; P-MOSFETS; STANDARD CMOS;

MOSFET DEVICES;

FINS (HEAT EXCHANGE);

EID: 76949095291     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.11.162     Document Type: Article

References (3)

1. Colinge J.P. FinFETs and Other Multi-Gate Transistors (2008), Springer, New York
2. Zaborowski M., and Grabiec P. Microelectronic Engineering 85 5-6 (2008) 1257-1260
3. Schroder D.K. Semiconductor Material and Device Characterization. third ed. (2006), John Wiley & Sons