3D opto-electrical device stacking on CMOS

Microelectronic Engineering

Volumn 87, Issue 5-8, 2010, Pages 1210-1212

  Dellmann, L ^a   Drechsler, U ^a   Morf, T ^a   Rothuizen, H ^a   Stutz, R ^a   Weiss, J ^a   Despont, M ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

3D packaging; CMOS; Heterogeneous device integration; III V; Opto electronic integration

Indexed keywords

3-D INTEGRATION; 3D PACKAGING; BACK END OF LINES; CMOS WAFERS; ELECTRICAL CHARACTERIZATION; ELECTRICAL DEVICES; FULLY COMPATIBLE; HETEROGENEOUS DEVICE INTEGRATION; HIGH POTENTIAL; I/O BANDWIDTH; INTEGRATION PROCESS; INTERCONNECT TECHNOLOGY; OPTO-ELECTRONICS; PLANARIZATION; TOP-EMITTING;

BANDWIDTH; THREE DIMENSIONAL;

INTEGRATION;

EID: 76949086872     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2009.11.170     Document Type: Article

References (4)

1. F. Doany et al., in: Proc. IEEE Electronic Components and Technology Conf., 2008, pp. 238-243.
2. Dangel R., et al. IEEE Trans. Adv. Pack. 31 4 (2008) 759-767
3. Despont M., et al. J. Microelectromech. Syst. 13 6 (2004) 895-901
4. .