Reducing peak power with a table-driven adaptive processor core

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 189-200

  Kontorinis, Vasileios ^a   Shayan, Amirali ^a   Kumar, Rakesh ^b   Tullsen, Dean M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Adaptive architectures; Decoupling capacitance; Peak power; Resource resizing; Voltage variation

Indexed keywords

ADAPTIVE ARCHITECTURE; ADAPTIVE PROCESSORS; AVERAGE POWER; CORE AREA; CURRENT PROCESSORS; DE-COUPLING CAPACITANCE; DECOUPLING CAPACITOR; DESIGN OPTION; PEAK POWER; PEAK-POWER CONSTRAINTS; PERFORMANCE LOSS; POWER DELIVERY; POWER DISSIPATION; PROCESSOR CORES; PROCESSOR DESIGN; VOLTAGE VARIATION;

CAPACITANCE; CAPACITANCE MEASUREMENT; ELECTRIC POWER TRANSMISSION;

COMPUTER ARCHITECTURE;

EID: 76749135281     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669137     Document Type: Conference Paper

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