Design space characterization for architecture/compiler co-exploration

CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2001, Pages 108-115

  Fischer, Dirk ^a   Teich, Jürgen ^a   Weper, Ralph ^a   Kastens, Uwe ^a   Thies, Michael ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

Design

Indexed keywords

DESIGN; EMBEDDED SYSTEMS; OPTIMAL SYSTEMS;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSOR; CODE GENERATION; CODE OPTIMIZATION; DESIGN SPACES; OPTIMAL ARCHITECTURE;

PROGRAM COMPILERS;

EID: 76749114656     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/502217.502234     Document Type: Conference Paper

References (22)

1. M. Anlauff. XASM - an extensible, component-based abstract state machines language. In Y. Gurevich, P. Kutter, M. Odersky, and L. Thiele, editors, International Workshop on Abstract State Machines, Lecture Notes on Computer Science (LNCS), pages 69-90. Springer, 2000.
2. M. Anlauff, D. Fischer, P. Kutter, J. Teich, and R. Weper. Hierarchical microprocessor design using XASM. In Formal Methods and Tools for Computer Science, Proceedings of the 8th International Conference on Computer Aided Systems Theory and Technology (EUROCAST 2001), pages 271-274, Las Palmas de Gran Canaria, Canary Islands, Spain, February 2001.
3. http://www-date.upb.de/RESEARCH/BUILDABONG/buildabong.html
4. http://www.ace.nl/products/cosy.html
5. A. Fauth. Beyond tool-specific machine descriptions. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, pages 138-152. Kluwer Academic Publishers, 1995.
6. A. Fauth, J. Van Praet, and M. Freericks. Describing instruction set processors using nML. In Proceedings on the European Design and Test Conference, Paris, France, pages 503-507, March 1995.
7. C. Fraser and D. Hanson. A retargetable C Compiler: Design and implementation. Addison-Wesley, 1995.
8. G. Goossens, J. Van Praet, D. Lanneer, W. Geurts, and F. Thoen. Programmable chips in consumer electronics and telecommunications. In G. de Micheli and M. Sami, editors, Hardware/Software Co-Design, volume 310 of NATO ASI Series E: Applied Sciences, pages 135-164. Kluwer Academic Publishers, 1996.
9. Y. Gurevich. Evolving algebras 1993: Lipari guide. In E. Börger, editor, Specification and Validation Methods, pages 9-36, Oxford University Press, 1995.
10. A. Halambi, P. Grun, A. Khare, V. Ganesh, N. Dutt, and A. Nicolau. Expression: A language for architecture exploration through compiler/simulator retargetability. In Proceedings Design Automation and Test in Europe (DATE'1999), 1999.
11. D. Kästner. Retargetable Postpass Optimisation by Integer Linear Programming. Pirrot Verlag, Saarbrücken, October 2000. Phd thesis.
12. http://ls12-www.informatik.uni-dortmund.de/fileupers/lanceV2/lanceV2.html
13. D. Lanneer, J. Van Praet, A. Kifli, K. Schoofs, W. Geurts, F. Thoen, and G. Goossens. Chess: Retargetable code generation for embedded dsp processors. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, pages 85-102. Kluwer Academic Publishers, 1995.
14. P. Paulin, C. Liem, T. May, and S. Sutarwala. Flexware: A flexible firmware development environment for embedded systems. In P. Marwedel and G. Goossens, editors, Code Generation for Embedded Processors, pages 67-84. Kluwer Academic Publishers, 1995.
15. S. Pees, A. Hoffmann, and H. Meyr. Retargeting of compiled simulators for digital signal processors using a machine description language. In Proceedings Design Automation and Test in Europe (DATE'2000), Paris, March 2000.
16. P. Pfahler and G. Piepenbrock. A Comparison of Modulo Scheduling Techniques for Software Pipelining. In Proc. 6th International Conference on Compiler Construction, CC'96, volume 1060, pages 18-32. Lecture Notes in Computer Science, Springer-Verlag, 1996.
17. T. A. Proebsting. BURS automata generation. ACM Transaction on Programming Languages and Systems, 17(3):461-486, May 1995.
18. E. Stümpel, M. Thies, and U. Kastens. VLIW compilation techniques for superscalar architectures. In K. Koskimies, editor, Proceedings 7th International Conference on Compiler Construction CC'98, number 1383 in Lecture Notes in Computer Science, pages 234-248. Springer, March 1998.
19. J. Teich, P. Kutter, and R. Weper. Description and simulation of microprocessor instruction sets using asms. In Y. Gurevich, P. Kutter, M. Odersky, and L. Thiele, editors, International Workshop on Abstract State Machines, Lecture Notes on Computer Science (LNCS), pages 266-286. Springer, 2000.
20. J. Teich, R. Weper, D. Fischer, and S. Trinkert. A joined architecture/compiler design environment for ASIPs. In ACM SIG Proceedings International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2000), pages 26-33, San Jose, CA, U.S.A., November 2000.
21. http://www.trimaran.org.
22. F. Wichmann and P. Pfahler. Compilation for fine-grained parallelism: A code generator for the intel i860. Technical report, University of Paderborn, October 1992. Internal Report tr-ri-92-105.