Boundary-scan adoption - An industry snapshot with emphasis on the semiconductor industry

Proceedings - International Test Conference

Volumn , Issue , 2009, Pages

  Geiger, Philip B ^a   Butkovich, Steve ^b  

^a DELL INC   (United States)

^b CISCO SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DENSITY; COST-EFFICIENT; ELECTRICAL TESTS; FUTURE DESIGNS; INTERNATIONAL ELECTRONICS MANUFACTURING INITIATIVE (INEMI); PRINTED CIRCUIT ASSEMBLIES; SEMICONDUCTOR INDUSTRY; SEMICONDUCTOR SUPPLIERS; TESTABILITY;

ELECTRONIC EQUIPMENT MANUFACTURE; PRINTED CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; SURVEYS; TESTING;

SEMICONDUCTOR INSULATOR BOUNDARIES;

EID: 76549134821     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2009.5355673     Document Type: Conference Paper

References (6)

1. Press release: "IEEE 1149.7 Standard Cuts Space, Cost for Embedded Systems," SMT, September 2008.
2. IEEE P1581 Working Group white paper, "An Economical Alternative to Boundary Scan in Memory Devices," http://grouper.ieee.org/groups/1581/
3. J.R. Purser, "JTAG Hacking", NetworkWorld online, Feb. 2008.
4. R.F. Buskey and B.B. Frosik, "Protected JTAG," Proceedings of the 2006 International Conference on Parallel Processing Workshops.
5. B. Eklow, C. Barnhart, M. Ricchetti, T. Borroz, "IEEE 1149.6 - A Practical Perspective," Proceedings of the 2003 International Test Conference.
6. "ARM-JTAG Wiggler Compatible Dongle for Programming And Debugging," 2004, OLIMEX Ltd.