Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2009, Pages 433-440

  Li, Xin ^a   Rutenbar, Rob R ^a   Blanton, Ronald D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Characterization; Integrated circuit; Process variation

Indexed keywords

COMPRESSED SENSING; ESTIMATION ERRORS; FREQUENCY DOMAINS; INDUSTRIAL MEASUREMENTS; LINEAR PROGRAMMING PROBLEM; MEASUREMENT DATA; NANO SCALE; NANOSCALE MANUFACTURING; NYQUIST RATE; PROCESS VARIATION; SAMPLING FREQUENCIES; SPATIAL VARIATIONS; VIRTUAL PROBES;

COMPUTER AIDED DESIGN; COST REDUCTION; DIES; INTEGRATED CIRCUITS; LINEARIZATION; NANOSTRUCTURED MATERIALS; PROBES;

SILICON WAFERS;

EID: 76349095539     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

1. S. Nassif, "Delay variability: sources, impacts and trends," IEEE ISSCC, pp. 368-369, 2000.
2. Semiconductor Industry Associate, International Technology Roadmap for Semiconductors, 2007.
3. H. Chang and S. Sapatnekar, "Statistical timing analysis under spatial correlations," IEEE Trans. CAD, vol. 24, no. 9, pp. 1467-1482, 2005.
4. C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker and S. Narayan, "First-order incremental block-based statistical timing analysis," IEEE DAC, pp. 331-336, 2004
5. Y. Zhan, A. Strojwas, X. Li, L. Pileggi, D. Newmark and M. Sharma, "Correlation aware statistical timing analysis with non-Gaussian delay distributions," IEEE DAC, pp. 77-82, 2005.
6. K. Heloue and F. Najm, "Statistical timing analysis with two-sided constraints," IEEE ICCAD, pp. 829-836, 2005.
7. M. Mani, A. Singh, and M. Orshansky, "Joint design-time and postsilicon minimization of parametric yield loss using adjustable robust optimization," IEEE ICCAD, pp. 19-26, 2006.
8. S. Kulkarni, D. Sylvester and D. Blaauw, "A statistical framework for post-silicon tuning through body bias clustering," IEEE ICCAD, pp. 39-46, 2006.
9. Q. Liu and S. Sapatnekar, "Synthesizing a representative critical path for post-silicon delay prediction," ACM ISPD, pp. 183-190, 2009.
10. M. Ketchen, M. Bhushan and D. Pearson, "High speed test structures for in-line process monitoring and model calibration," IEEE ICMTS, pp. 33-38, 2005.
11. M. Bhushan, A. Gattiker, M. Ketchen and K. Das, "Ring oscillators for CMOS process tuning and variability control," IEEE Trans. Semiconductor Manufacturing, vol. 19, no. 1, pp. 10-18, Feb. 2006.
12. W. Mann, F. Taber, P. Seitzer and J. Broz, "The leading edge of production wafer probe test technology," IEEE ITC, pp. 1168-1195, 2004.
13. F. Koushanfar, P. Boufounos and D. Shamsi, "Post-silicon timing characterization by compressed sensing," IEEE ICCAD, pp. 185-189, 2008.
14. S. Reda and S. Nassif, "Analyzing the impact of process variations on parametric measurements: novel models and applications," IEEE DATE, pp. pp. 375-380, 2009.
15. R. Tibshirani, "Regression shrinkage and selection via the Lasso," Journal of Royal Statistical Society, vol. 58, no. 1, pp. 267-288, 1996.
16. E. Candes, "Compressive sampling," International Congress of Mathematicians, 2006.
17. D. Donoho, "Compressed sensing," IEEE Trans. Information Theory, vol. 52, no. 4, pp. 1289-1306, Apr. 2006.
18. A. Oppenheim, Signals and Systems, Prentice Hall, 1996.
19. M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
20. S. Boyd and L. Vandenberghe, Convex Optimization, Cambridge University Press, 2004.
21. C. Bishop, Pattern Recognition and Machine Learning, Prentice Hall, 2007.
22. R. Gonzalez and R. Woods, Digital Image Processing, Prentice Hall, 2007.
23. W. Press, S. Teukolsky, W. Vetterling and B. Flannery, Numerical Recipes: The Art of Scientific Computing, Cambridge University Press, 2007.