Evolution of deep submicron bulk and SOI technologies

Low-Power Electronics Design

Volumn , Issue , 2004, Pages 2-1-2-16

  Belleville, Marc ^a   Faynot, Olivier ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 7544249998     PISSN: None     EISSN: None     Source Type: Book    
DOI: None     Document Type: Chapter

References (41)

1. B. Doris et al. Extreme scaling with ultra-thin Si channel MOSFETs, IEDM’02, Tech. Dig., pp. 267–270, 2002.
2. D. J. Frank et al. Device scaling limits of SiMOSFETs and their application dependencies, Proc. IEEE, Vol. 89, No. 3, March 2001.
3. The International Technology Roadmap for semiconductors, 2001 and 2002 update, http://public.itrs.net.
4. C. Raynaud, SOI Process Integration, Short Course, IEEE SOI Conf., Durango, Colorado, October 2001.
5. L. E. Thon et al. 250–600 MHz 12b digital filters in 0.8–0.25 mm bulk and SOI CMOS technologies, Int. Symp. on Low-Power Electronics, pp. 89–92, 12–14 August 1996.
6. M. Itoh et al. Fully depleted SIMOX SOI process technology for low-power digital and RF device, Silicon on Insulator Technology and Devices, Proc. 10th Int. Symp. Electrochemical Society, Washington, D.C., March 25–29, 2001, pp. 331—336.
7. K. Gopalakrishnan et al. I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q, IEDM Tech. Dig., pp. 289–292, 2002.
8. T. Kuroda et al. “Variable threshold-voltage CMOS technology, IEICE Trans. Electron., Vol. E83-C, No. 11, November 2000.
9. A. Keshavarzi et al. Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s, ISLPED’99, San Diego, California, August 16–17, 1999, pp. 252–254.
10. S. Mutoh et al. 1-V high-speed digital circuit technology with 0.5 mm multi-threshold CMOS, ASIC Conf. and Exhibit, September 27–October 1, 1993, pp. 186–189.
11. T. Kuroda et al. Optimization and control of VDD and Vth for low-power, high-speed CMOS design, ICCAD’02, November 2002, pp. 28-34.
12. A. Abdollahi et al. Runtime mechanisms for leakage current reduction in CMOS VLSI circuits, ISPLED’02, August 12–14, Monterey, CA, pp. 213—218.
13. T. Douseki et al. A 0.5-V SIMOX–MTCMOS circuit with 200 ps logic gate, Solid-State Circuits Conf., 1996. Digest of Technical Papers, pp. 84–85, February 1996.
14. F. Morishita et al. Dynamic floating body control SOI CMOS for power-managed multimedia ULSIs, IEICE Trans. Electron., Vol. E84-C, No. 2, pp. 253–259, February 2001.
15. Y. Naveh et al. Modeling of 10-nm scale ballistic MOSFETs, IEEE Electron. Device Lett., 21, 242–244, 2000.
16. J. D. Plummer et al. Material and process limits in silicon VLSI technology, Proc. IEEE, Vol. 89, No. 3, March 2001.
17. S. H. Lo et al. Quantum mechanical modeling of electron tummeling current from the inversion layer of ultra-thin-oxide nMOSFETs, IEEE Electron. Device Lett., 18, 209–211, 1997.
18. W. C. Lee et al. Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling, VLSI Symp., 2000, pp. 198–199.
19. F. Hamzaoglu et al. Circuit-level techniques to control gate leakage for sub-100nm CMOS, ISPLED’02, August 12–14, Monterey, CA, pp. 60–63.
20. A. L. P. Rotondaro et al. Advanced CMOS transistors with a novel HfSiON Gate dielectric, VLSI Symp. 2002, Tech. Dig., p. 148.
21. S. A. Campbell et al. MOSFET transistors fabricated with high permitivity Ti02 dielectrics, IEEE Trans. on Electron. Devices, Vol. 44, p. 104, 1997.
22. D. J. Frank et al. Generalized scale length for two-dimensional effects in SOI MOSFETs, IEEE Electron. Device Lett., Vol. 19, pp. 385–387, October 1998.
23. B. Guillaumot et al. 75-nm damascene metal gate and high K integration for advanced CMOS devices, IEDM’02, Tech. Dig., pp. 355–358, 2002.
24. H. S. Wong et al., Three-dimensional atomistic simulation of discrete microscopic random dopant distributions effects in nanometer-scale MOSFETs, Microelectron. Reliability, 38, 1447–1456, 1998.
25. H. S. Wong et al. Discrete random dopant distribution effects in nanometer-scale MOSFETs, Microelectron. Reliability, 38, 1447–1456, 1998.
26. D. J. Frank et al. Monte Carlo modeling of threshold variation due to dopant fluctuations, Symp. on VLSI Technol., Dig. of Tech. Papers, pp. 1169–170, 1999.
27. M. Kishor et al. Threshold voltage and power supply tolerance of CMOS logic design families, Symp. on Defect and Fault Tolerance in VLSI Systems, October 25–27, 2000, Yamanashi, Japan, pp. 349–357.
28. M. Eisele et al. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits, IEEE Trans. on VLSI Systems, Vol. 5, No. 4, pp. 360–368, December 1997.
29. D. Burnett et al. Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits, Symp. on VLSI Technol., 1994, pp. 15–16.
30. A. Asenov, Efficient 3D “atomistic” simulation technique for studying of random dopant induced threshold voltage lowering and fluctuations in decanano MOSFETs, 6th Int. Workshop on Computational Electronics, 1998, pp. 263–266.
31. J. D. Plummer et al. Material and process limits in silicon VLSI technology, Proc. IEEE, Vol. 89, No. 3, pp. 240–258, 2001.
32. Y. Taur et al. 25-nm CMOS design considerations, Int. Electron. Devices Meeting, IEDM’98, December 6–9, 1998, pp. 789–792.
33. M. V. Fischetti et al. Band structure, deformation potentials, and varrier mobility in strained Si, Ge, and SiGe alloys, J. Appl. Phys., Vol. 80, No. 4, pp. 2234–2252, 1996.
34. F. Andrieu et al. “SiGe channel p-MOSFETs scaling-down, to be published at ESSDERC’03, Estoril, Portugal, September 16–18, 2003, pp. 267–270.
35. K. Rim et al. Strained Si MOSFETs for high-performance CMOS technology, Symp. on VLSI Technol. pp. 59–60, 2001.
36. H. S. P. Wong et al. Self-Aligned (Top and Bottom) Double Gate MOSFET with a 25nm Thick Silicon Channel, IEDM Tech. Dig., 1997, pp. 427–430.
37. J. T. Park et al. Pi-gate SOI MOSFET, IEEE Electron. Dev. Lett., Vol. 22, No. 8, pp. 405–408, 2000.
38. D. Hisamoto et al. FinFET- A self-Aligned Double-Gate MOSFET Scalable to 20nm, IEEE Trans. Electron Dev., Vol. 47, No. 12, pp. 2320–2325, 2000.
39. J. P. Colinge et al. Silicon-on-Insulator Gate-All-Around device, IEDM Tech. Dig., pp. 595-598, 1990.
40. J. H. Lee et al. Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy, IEDM Tech. Dig., 1999.
41. Y. K. Choi et al. FinFET process refinements for improved mobility and gate work function engineering, IEDM Tech. Dig., pp. 259–262, 2002.