xMAML: A modeling language for dynamically reconfigurable architectures

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 680-687

  Lallet, Julien ^a   Pillement, Sébastien ^a   Sentieys, Olivier ^a  

^a CAMPUS DE BEAULIEU   (France)

Author keywords

ADL; Dynamic reconfiguration

Indexed keywords

ARCHITECTURE DESCRIPTION LANGUAGES; DESIGN FRAMEWORKS; DYNAMIC RE-CONFIGURATION; DYNAMICALLY RECONFIGURABLE ARCHITECTURE; FRONT-END TOOLS; HETEROGENEOUS COMPUTING; HIGH LEVEL ARCHITECTURE; MODELING LANGUAGES; PROOF OF CONCEPT; RE-CONFIGURABLE; SIMULATION AND VALIDATION; SYSTEM-ON-CHIP; WCDMA RECEIVERS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; DYNAMIC MODELS; HIERARCHICAL SYSTEMS; LINGUISTICS; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; QUERY LANGUAGES; SYSTEMS ANALYSIS;

HIGH LEVEL LANGUAGES;

EID: 74549152739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.151     Document Type: Conference Paper

References (17)

1. A. Kupriyanov, F. Hannig, K. Dmitrij, J. Teich, J. Lallet, S. Pillement, and O. Sentieys. Modeling of Interconnection Networks in Massively Parallel Processor Architectures. In 20th International Conference on Architecture of Computing Systems (ARCS), pages 268-282, 2007.
2. H. Amano. A survey on dynamically reconfigurable processors. IEICE TRANSACTIONS on Communications, E89-B(12):3179-3187, Dec. 2006.
3. S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedel, A. Neumann, and D. Voggenauer. The mimola language - version 4.1, 1994.
4. V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
5. F. Charot and V. Messe. A flexible code generation framework for the design of application specific programmable processors. In International workshop on Hardware/Software Codesign, pages 27-32, 1999.
6. A. Fauth, J. V. V. Praet, and M. Freericks. Describing instruction set processors using nml. In European conference on Design and Test, 1995.
7. G. Hadjiyiannis, S. Hanono, and S. Devadas. Isdl: an instruction set description language for retargetability. In 34th annual conference on Design automation, pages 299-302, 1997.
8. M. Hariyama, W. Chong, S. Ogata, and M. Kameyama. Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. In IEEE Computer Society Annual Symposium On VLSI (ISVLSI), pages 46-50, 2005.
9. A. Hoffmann, H. Meyr, and R. Leupers. Architecture Exploration for Embedded Processors with Lisa. Kluwer Academic Publishers, Norwell, 2002.
10. O. Karatsu. Udl/i standardization effort another approach to hdl standard. In Euro ASIC, pages 388-393, 1991.
11. D. Kawakami, Y. Shibata, and H. Amano. A prototype chip of multicontext FPGA with DRAM for Virtual Hardware. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 17-18, 2001.
12. D. Koch, A. Ahmadinia, C. Bobda, H. Kalte, and J. Teich. FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation. In IEEE Conference on Field-Programmable Technology (FPT), pages 433-436, 2004.
13. L. Lagadec and B. Pottier. Object-Oriented Meta Tools for Reconfigurable Architectures. In Reconfigurable Technology: FPGAs for Computing and Applications II, volume 4212, pages 69-79. SPIE, 2000.
14. J. Lallet, S. Pillement, and O. Sentieys. Efficient dynamic reconfiguration for multi-context embedded fpga. In Symposium on Integrated Circuits and Systems Design (SBCCI), 2008.
15. T. Ojanpera and R. Prasad. Wideband CDMA For Third Generation Mobile Communication. Artech House Publishers, 1998.
16. S. Pillement, R. David, and O. Sentieys. Dart : A functional-level reconfigurable architecture for high energy efficiency. EURASIP Journal on Embedded Systems, 2008:13, 2007.
17. Xilinx. XC4000E and XC4000X Series Field Programmable Gate Arrays, May 1999.