Hardware architecture for HOG feature extraction

IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing

Volumn , Issue , 2009, Pages 1330-1333

  Kadota, Ryoji ^a   Sugano, Hiroki ^a   Hiromoto, Masayuki ^a   Ochi, Hiroyuki ^a   Miyamoto, Ryusuke ^b   Nakamura, Yukihiro ^c  

^a KYOTO UNIVERSITY   (Japan)

^b NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^c RITSUMEIKAN UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIZE; DETECTION PERFORMANCE; HARDWARE ARCHITECTURE; HIGH-ACCURACY; PEDESTRIAN RECOGNITION; PROCESSING PERFORMANCE; PROPOSED ARCHITECTURES; REALTIME PROCESSING; RECOGNITION ACCURACY; SIMPLE OPERATION; SQUARE ROOTS; VERILOG HDL;

COMPUTATIONAL COMPLEXITY; EMBEDDED SYSTEMS; FEATURE EXTRACTION; REAL TIME SYSTEMS; SIGNAL PROCESSING;

MULTIMEDIA SIGNAL PROCESSING;

EID: 73649137144     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IIH-MSP.2009.216     Document Type: Conference Paper

References (4)

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