Effects of interfacial dielectric layers on the electrical performance of top-gate In-Ga-Zn-oxide thin-film transistors

ETRI Journal

Volumn 31, Issue 6, 2009, Pages 660-666

  Cheong, Woo Seok ^a   Lee, Jeong Min ^a   Lee, Jong Ho ^b   Park, Sang Hee Ko ^a   Yoon, Sung Min ^a   Byun, Chun Won ^a   Yang, Shinhyuk ^a   Chung, Sung Mook ^a   Cho, Kyoung Ik ^a   Hwang, Chi Sun ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b Kyungpook National University   (South Korea)

Author keywords

Electrical stability; IGZO; Interfacial dielectric layer; Thin film transistor

Indexed keywords

ATOMIC RATIO; BIAS STRESS; BROKEN BONDS; COMPENSATION EFFECTS; CONSTANT-CURRENT STRESS; DIELECTRIC LAYER; ELECTRICAL PERFORMANCE; ELECTRICAL PROPERTY; ELECTRICAL STABILITY; GOOD STABILITY; INTERFACIAL TRAPS; LOW TEMPERATURES; POST ANNEALING; SI-BASED; SUBTHRESHOLD SWING; TARGET COMPOSITION; TOP-GATE;

ELECTRIC PROPERTIES; GALLIUM; SEMICONDUCTING ORGANIC COMPOUNDS; SILICON; THIN FILM TRANSISTORS; ZINC;

DIELECTRIC MATERIALS;

EID: 73449139107     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.09.1209.0049     Document Type: Article

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