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Volumn 57, Issue 1, 2010, Pages 222-227

Sub-1-V CMOS image sensor using time-based readout circuit

Author keywords

CMOS active pixel sensor; CMOS image sensor (CIS); Low power; Low voltage; Time based readout (TBR)

Indexed keywords

CMOS ACTIVE PIXEL SENSORS; CMOS IMAGE SENSOR; DYNAMIC RANGE; GATE TRANSISTORS; LOW POWER; MEASUREMENT RESULTS; POWER SUPPLY VOLTAGE; PROTOTYPE CHIP; READ-OUT CIRCUIT; STANDARD CMOS; VOLTAGE SIGNALS;

EID: 73349112852     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2035194     Document Type: Article
Times cited : (15)

References (12)
  • 1
    • 0031249402 scopus 로고    scopus 로고
    • CMOS image sensors: Electronic camera-on-a-chip
    • t.
    • E. R. Fossum, "CMOS image sensors: Electronic camera-on-a-chip, " IEEE Trans. Electron Devices, vol.44, no.10, pp. 1689-1698, Oct. 1997.
    • (1997) IEEE Trans. Electron Devices , vol.44 , Issue.10 , pp. 1689-1698
    • Fossum, E.R.1
  • 2
    • 53649084498 scopus 로고    scopus 로고
    • A dual-capture wide dynamic range CMOS image sensor using floating diffusion capacitor
    • Oct.
    • D. Kim, Y. Chae, J. Cho, and G. Han, "A dual-capture wide dynamic range CMOS image sensor using floating diffusion capacitor," IEEE Trans. Electron Devices, vol.55, no.10, pp. 2590-2594, Oct. 2008.
    • (2008) IEEE Trans. Electron Devices , vol.55 , Issue.10 , pp. 2590-2594
    • Kim, D.1    Chae, Y.2    Cho, J.3    Han, G.4
  • 4
    • 57149140608 scopus 로고    scopus 로고
    • Low noise in-pixel comparing active pixel sensor using column-level single-slope ADC
    • Dec.
    • D. Lee, K. Cho, D. Kim, and G. Han, "Low noise in-pixel comparing active pixel sensor using column-level single-slope ADC," IEEE Trans. Electron Devices, vol.55, no.12, pp. 3383-3388, Dec. 2008.
    • (2008) IEEE Trans. Electron Devices , vol.55 , Issue.12 , pp. 3383-3388
    • Lee, D.1    Cho, K.2    Kim, D.3    Han, G.4
  • 5
    • 49549089342 scopus 로고    scopus 로고
    • A CMOS image sensor integrating column-parallel cyclic ADCs with onchip digital error correction circuits
    • Feb.
    • S. Kawahito, J. Park, K. Isobe, S. Shafie, T. Lida, and T. Mizota, "A CMOS image sensor integrating column-parallel cyclic ADCs with onchip digital error correction circuits," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 56-57.
    • (2008) In Proc. IEEE ISSCC Dig. Tech. Papers , pp. 56-57
    • Kawahito, S.1    Park, J.2    Isobe, K.3    Shafie, S.4    Lida, T.5    Mizota, T.6
  • 7
    • 33845620276 scopus 로고    scopus 로고
    • A CMOS imager with column-level ADC using dynamic column fixed-pattern noise reduction
    • DOI 10.1109/JSSC.2006.884866
    • M. Snoeij, A. P. Theuwissen, K. Makinwa, and J. Huijsing, "A CMOS imager with column-level ADC using dynamic column fixed-pattern noise reduction," IEEE J. Solid-State Circuits, vol.41, no.12, pp. 3007-3015, Dec. 2006. (Pubitemid 44955526)
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.12 , pp. 3007-3015
    • Snoeij, M.F.1    Theuwissen, A.J.P.2    Makinwa, K.A.A.3    Huijsing, J.H.4
  • 8
    • 0037253141 scopus 로고    scopus 로고
    • A 1.5-V 550- μw 176 × 144 autonomous CMOS active pixel image sensor
    • Jan.
    • K. B. Cho, A. Krymski, and E. R. Fossum, "A 1.5-V 550- μW 176 × 144 autonomous CMOS active pixel image sensor," IEEE Trans. Electron Devices, vol.50, no.1, pp. 96-105, Jan. 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.1 , pp. 96-105
    • Cho, K.B.1    Krymski, A.2    Fossum, E.R.3
  • 9
    • 49549096718 scopus 로고    scopus 로고
    • A 3.6 pW/frame pixel 1.35 v PWM CMOS imager with dynamic pixel readout and no static bias current
    • Feb.
    • K. Kagawa, S. Shishido, M. Nunoshita, and J. Ohto, "A 3.6 pW/frame pixel 1.35 V PWM CMOS imager with dynamic pixel readout and no static bias current," in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 54-55.
    • (2008) In Proc. IEEE ISSCC Dig. Tech. Papers , pp. 54-55
    • Kagawa, K.1    Shishido, S.2    Nunoshita, M.3    Ohto, J.4
  • 12
    • 36448940197 scopus 로고    scopus 로고
    • High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers
    • Nov.
    • D. Lee and G. Han, "High-speed, low-power correlated double sampling counter for column-parallel CMOS imagers," Electron. Lett., vol.43, no.24, pp. 1362-1364, Nov. 2007.
    • (2007) Electron. Lett , vol.43 , Issue.24 , pp. 1362-1364
    • Lee, D.1    Han, G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.