A flexible parallel simulator for networks-on-chip with error control

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 1, 2010, Pages 103-116

  Yu, Qiaoyan ^a   Ampadu, Paul ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

Error control; Fault tolerance; Networks on chip; Performance analysis and design aid; Reliability; Simulator

Indexed keywords

DESIGN GUIDELINES; ENERGY CONSUMPTION; ERROR CONTROL; FAULT INJECTION; FAULT TYPES; FLEXIBLE SIMULATION; NETWORKS ON CHIPS; NETWORKS-ON-CHIP; PARALLEL SIMULATOR; PERFORMANCE ANALYSIS AND DESIGN AID; PLUG-AND-PLAY;

BIOLOGICAL MATERIALS; ELECTRIC NETWORK TOPOLOGY; QUALITY ASSURANCE; RELIABILITY ANALYSIS; SIMULATORS; SOFTWARE TESTING;

FAULT TOLERANCE;

EID: 73249147858     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2034353     Document Type: Article

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