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Volumn 18, Issue 1, 2010, Pages 29-38

A VLSI architecture and algorithm for Lucas-Kanade-based optical flow computation

Author keywords

Field programmable gate array (FPGA) implementation; Lucas Kanade algorithm; Optical flow; VLSI architecture

Indexed keywords

APPLICATION-SPECIFIC SYSTEMS; BIT-WIDTH; COMPUTATIONAL POWER; DATA FLOW; FIELD-PROGRAMMABLE GATE ARRAY (FPGA) IMPLEMENTATION; FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS; GAUSSIAN SMOOTHING; GRADIENT COMPUTATION; HARDWARE IMPLEMENTATIONS; HIGH RESOLUTION; HIGH-SPEED; K ALGORITHM; LEAST SQUARE; LUCAS-KANADE ALGORITHM; OPTIC FLOW; OPTICAL FLOW COMPUTATION; OPTICAL FLOW ESTIMATION; PROPOSED ARCHITECTURES; REALTIME PROCESSING; SPEED-UPS; STORAGE AREA; SYSTEM RESOURCES; VELOCITY ESTIMATION; VISION-BASED SYSTEM; VLSI ARCHITECTURES;

EID: 73249142569     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2006900     Document Type: Article
Times cited : (44)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.