Topology comparison and design optimisation of the buck converter and the single-inductor dual-output converter for system-in-package in 65nm CMOS

2009 IEEE 6th International Power Electronics and Motion Control Conference, IPEMC '09

Volumn , Issue , 2009, Pages 295-301

  Haizoune, F ^a   Bergveld, H J ^b   Popovic Gerber J ^a   Ferreira, J A ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; ACTIVE PARTS; ALTERNATIVE TECHNOLOGIES; BATTERY LIFE; BUCK CONVERTERS; CHIP SIZES; CIRCUIT TOPOLOGY; DESIGN OPTIMISATION; DESIGN OPTIMIZATION; DESIGN PROCEDURE; ELECTRICAL CURRENT; HIGH EFFICIENCY; HIGH OPERATING FREQUENCY; HIGH-POWER-DENSITY; HYBRID INTEGRATION; INTEGRATION TECHNOLOGIES; LI-ION BATTERIES; LOAD CURRENTS; MONOLITHIC INTEGRATION; PASSIVE COMPONENTS; PORTABLE ELECTRONIC DEVICES; POWER ELECTRONIC CONVERTERS; POWER SEMICONDUCTOR LOSS; POWER SEMICONDUCTORS; SWITCHING LOSS; SYSTEM IN PACKAGE; SYSTEM ON CHIPS; TRANSISTOR WIDTH; WAVE FORMS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DC-DC CONVERTERS; DESIGN; ELECTRIC NETWORK TOPOLOGY; HVDC POWER TRANSMISSION; INTEGRATION; LAPTOP COMPUTERS; LITHIUM BATTERIES; MOTION CONTROL; MOTION PLANNING; OPTIMIZATION; PORTABLE EQUIPMENT; TECHNOLOGY; THERMOELECTRIC EQUIPMENT;

POWER ELECTRONICS;

EID: 72449183891     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPEMC.2009.5157402     Document Type: Conference Paper

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