A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration

2009 IEEE Energy Conversion Congress and Exposition, ECCE 2009

Volumn , Issue , 2009, Pages 3698-3705

  Bergveld, Henk Jan ^a   Nowak, Katarzyna ^a   Karadi, Ravi ^a   Iochem, Sebastien ^b   Ferreira, Jorge ^b   Ledain, Sophie ^b   Pieraerts, Eric ^b   Pommier, Mickael ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b NXP SEMICONDUCTORS   (France)

Author keywords

CMOS integrated circuits; DC DC power conversion; Microassembly; Packaging; Passive circuits; Pulse width modulated power converters

Indexed keywords

ACTIVE CONVERTERS; ALTERNATIVE APPROACH; DC-DC POWER CONVERSION; DOWN CONVERTERS; HIGH QUALITY; HIGH-DENSITY; INTEGRATED PASSIVES; INTEGRATION PROCESS; MICRO ASSEMBLY; MONOLITHICALLY INTEGRATED; MW OUTPUT; PASSIVE CIRCUITS; PASSIVE COMPONENTS; PEAK EFFICIENCY; POWER EFFICIENCY; PULSEWIDTH-MODULATED POWER CONVERTERS; SILICON AREA; SMALL SYSTEMS; STORAGE DENSITIES; SYSTEM IN PACKAGE; VOLTAGE CONVERSION;

CELLULAR RADIO SYSTEMS; CONTROL SYSTEM STABILITY; DC-DC CONVERTERS; DIES; ELECTRIC POWER MEASUREMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONVERSION; INTEGRATED CIRCUITS; LUMPED PARAMETER NETWORKS; MOS CAPACITORS; PACKAGING; PASSIVE NETWORKS; PULSE WIDTH MODULATION; SWITCHING FREQUENCY;

CMOS INTEGRATED CIRCUITS;

EID: 72449140593     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECCE.2009.5316334     Document Type: Conference Paper

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