Soft-error rate in a logic LSI estimated from SET pulse-width measurements

IEEE Transactions on Nuclear Science

Volumn 56, Issue 6, 2009, Pages 3180-3184

  Makino, Takahiro ^a,b   Kobayashi, Daisuke ^a,c   Hirose, Kazuyuki ^a,c   Takahashi, Daisuke ^d   Ishii, Shigeru ^d   Kusano, Masaki ^d   Onoda, Shinobu ^b   Hirao, Toshio ^b   Ohshima, Takeshi ^b  

^a GRADUATE UNIVERSITY FOR ADVANCED STUDIES   (Japan)

^b JAPAN ATOMIC ENERGY AGENCY   (Japan)

^c JAPAN AEROSPACE EXPLORATION AGENCY   (Japan)

^d MITSUBISHI HEAVY INDUSTRIES LTD   (Japan)

Author keywords

Logic cell; Single event transient; Soft error rate; SOI

Indexed keywords

LOGIC CELLS; PULSEWIDTHS; SINGLE EVENT TRANSIENTS; SOFT ERROR RATE;

LOGIC CIRCUITS; LOGIC DEVICES; LSI CIRCUITS;

TRANSIENTS;

EID: 72349095182     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2009.2033795     Document Type: Conference Paper

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