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Volumn , Issue , 2009, Pages

From algorithm to ASIC: Realising distortion tolerant transmission

Author keywords

[No Author keywords available]

Indexed keywords

CHIPSET; DIGITAL EQUALIZERS; DISTORTION TOLERANT; FIELD APPLICATION; FUNCTIONAL BLOCK; TWO-PRODUCT;

EID: 71949125324     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (6)
  • 2
    • 71949128990 scopus 로고    scopus 로고
    • Enhanced Equalization and Clock Recovery Concepts
    • N. Stojanovic et al. "Enhanced Equalization and Clock Recovery Concepts" ITG 3.5.1 Workshop, Berlin (2005)
    • (2005) ITG 3.5.1 Workshop, Berlin
    • Stojanovic, N.1
  • 4
    • 22744452342 scopus 로고    scopus 로고
    • Performance of a 10.7 Gb/s Receiver with Digital Equaliser using Maximum Likelihood Sequence Estimation
    • ECOC, PDTh4.1.5, Stockholm
    • A. Färbert et al. "Performance of a 10.7 Gb/s Receiver with Digital Equaliser using Maximum Likelihood Sequence Estimation" ECOC, PDTh4.1.5, Stockholm (2004)
    • (2004)
    • Färbert, A.1
  • 6
    • 71949118982 scopus 로고    scopus 로고
    • T. Kupfer et al, Measurement of the Performance of 16-States MLSE Digital Equalizer with Different Optical Modulation Formats, OFC 2008, PDP-13 (2008)
    • T. Kupfer et al, "Measurement of the Performance of 16-States MLSE Digital Equalizer with Different Optical Modulation Formats", OFC 2008, PDP-13 (2008)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.