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Volumn 30, Issue 10, 2009, Pages

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

Author keywords

CMOS; Gigabit Ethernet; Transimpedance amplifier

Indexed keywords

EYE DIAGRAMS; GAIN-BANDWIDTH PRODUCTS; GIGABIT ETHERNET; INPUT NOISE; INPUT RESISTANCE; PARASITIC CAPACITANCE; PHOTODIODE CAPACITANCE; POLE CANCELLATION; RF CMOS TECHNOLOGY; SIMULATION RESULT; TESTING RESULTS; TRANS-IMPEDANCE GAIN; TRANSIMPEDANCE AMPLIFIERS;

EID: 71249125674     PISSN: 16744926     EISSN: None     Source Type: Journal    
DOI: 10.1088/1674-4926/30/10/105005     Document Type: Article
Times cited : (17)

References (13)
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    • Changliang, Y.1    Luhong, M.2    Haobo, Z.3
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    • A monolithic GaAs receiver for optical interconnect systems
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  • 8
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    • Design and fabrication of 60-Gb/s InP-based monolithic photoreceiver OEIC's and modules
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    • Bach, H.G.1    Beling, A.2    Mekonnen, G.C.3
  • 9
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    • CMOS tunable TIA for 1.25 Gb/s optical gigabit ethernet
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    • Garcia, J.M.1    Celma, S.2    Sanz, M.T.3
  • 12
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    • 1 Gb/s CMOS photoreceiver with integrated detector operating at 850 nm
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  • 13
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    • 1.25 Gb/s regulated cascode CMOS transimpedance amplifier for gigabit ethernet applications
    • Park S M, Yoo H J 2004 1.25 Gb/s regulated cascode CMOS transimpedance amplifier for gigabit ethernet applications IEEE J. Solid-State Circuits 39 (1) 112
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    • Park, S.M.1    Yoo, H.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.