Reconfiguring crypto hardware accelerators on wireless sensor nodes

2009 6th IEEE Annual Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks Workshops, SECON Workshops 2009

Volumn , Issue , 2009, Pages

  Peter, Steffen ^a   Stecklina, Oliver ^a   Portilla, Jorge ^b   La Torre, Eduardo De ^b   Langendoerfer, Peter ^a   Riesgo, Teresa ^b  

^a IHP   (Germany)

^b UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

Elliptic curve cryptography; FPGA; Reconfigurability; Wireless sensor nodes

Indexed keywords

CRYPTO HARDWARE; CRYPTOGRAPHIC ALGORITHMS; ELLIPTIC CURVE; ELLIPTIC CURVE CRYPTOGRAPHY; EXECUTION TIME; FPGA; HARDWARE ACCELERATORS; MODULAR DESIGNS; PARTIAL RECONFIGURATION; POWER CONSUMPTION; RECONFIGURABILITY; REDUCTION UNIT; SPARTAN-3; SPEED-UPS; WIRELESS SENSOR NODE; WIRELESS SENSOR NODES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION; CRYPTOGRAPHY; ELECTRIC NETWORK SYNTHESIS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GEOMETRY; SENSOR NODES; SENSORS; TECHNICAL PRESENTATIONS; TELECOMMUNICATION EQUIPMENT;

AD HOC NETWORKS;

EID: 71049191406     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SAHCNW.2009.5172959     Document Type: Conference Paper

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