Parallel multi-confined (PMC) cell technology for high density MLC PRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 220-221

  Oh, G H ^a   Park, Y L ^a   Lee, J I ^a   Im, D H ^a   Bae, J S ^a   Kim, D H ^a   Ahn, D H ^a   Horii, H ^a   Park, S O ^a   Yoon, H S ^a   Park, I S ^a   Ko, Y S ^a   Chung, U In ^a   Moon, J T ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED CURRENT; CELL STRUCTURE; CELL TECHNOLOGY; DESIGN RULES; DRIFT COEFFICIENT; HIGH DENSITY; RESISTANCE LEVEL; SIMULATION RESULT;

CHEMICAL VAPOR DEPOSITION;

EID: 71049175383     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D.H. Kang et al., Symp. VLSI Tech dig., p. 17, 2008.
2. D.H. Im et al., IEDM, p. 211 , 2008.
3. S.L. Cho et al., Symp. VLSI Tech dig., p. 96, 2005.
4. J. I. Lee et al., Symp. VLSI Tech dig., p. 102, 2007