Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 138-139

  Choi, K ^a   Jagannathan, H ^b   Choi, C ^c   Edge, L ^b   Ando, T ^c   Frank, M ^c   Jamison, P ^c   Wang, M ^c   Cartier, E ^c   Zafar, S ^c   Bruley, J ^c   Kerber, A ^a   Linder, B ^c   Callegari, A ^c   Yang, Q ^c   Brown, S ^c   Stathis, J ^c   Iacoponi, J ^a   Paruchuri, V ^b   Narayanan, V ^c  

^a ADVANCED MICRO DEVICES   (United States)

^b IBM RESEARCH   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE PARAMETERS; GATE LEAKAGES; GATE STACK TECHNOLOGY; GATE STACKS; INTERFACIAL LAYER; SCALED DEVICES; TECHNOLOGY NODES; UNDERLYING MECHANISM;

CARRIER MOBILITY; LOGIC GATES; NANOTECHNOLOGY;

TECHNOLOGY;

EID: 71049123294     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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