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Volumn 2, Issue , 2009, Pages 48-55

Rotation scheduling and voltage assignment to minimize energy for SoC

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE BODY BIASING; CRITICAL ISSUES; DSP BENCHMARKS; DYNAMIC VOLTAGE SCALING; EMBEDDED SYSTEMS DESIGN; ENERGY SAVING; FEATURE SIZES; INTEGER LINEAR PROGRAMMING; LEAKAGE ENERGIES; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; LOW ENERGY CONSUMPTION; POWER CONSUMPTION; POWER MODEL; ROTATION SCHEDULING; SOFT REAL TIME; SYSTEMS ON CHIPS; TOTAL POWER CONSUMPTION; VOLTAGE ASSIGNMENT; VOLTAGE TRANSITION;

EID: 70749141579     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSE.2009.153     Document Type: Conference Paper
Times cited : (23)

References (20)
  • 1
    • 34547172837 scopus 로고    scopus 로고
    • Leakage-aware intraprogram voltage scaling for embedded processors
    • P. Huang and S. Ghiasi, "Leakage-aware intraprogram voltage scaling for embedded processors," in DAC, pp. 364-369, 2006.
    • (2006) DAC , pp. 364-369
    • Huang, P.1    Ghiasi, S.2
  • 2
    • 33745174527 scopus 로고    scopus 로고
    • Power reduction techniques for microprocessor systems
    • Sep.
    • V. Venkatachalam and M. Franz, "Power reduction techniques for microprocessor systems," ACM Computing Surveys (CSUR), vol. 37, pp. 195-237, Sep. 2005.
    • (2005) ACM Computing Surveys (CSUR) , vol.37 , pp. 195-237
    • Venkatachalam, V.1    Franz, M.2
  • 4
    • 34547234148 scopus 로고    scopus 로고
    • Methods for power optimization in distributed embedded systems with realtime requirements
    • Oct.
    • R. Racu, A. Hamann, R. Ernst, B. Mochocki, and X. Hu, "Methods for power optimization in distributed embedded systems with realtime requirements," in CASES'06, pp. 379-388, Oct. 2006.
    • (2006) CASES'06 , pp. 379-388
    • Racu, R.1    Hamann, A.2    Ernst, R.3    Mochocki, B.4    Hu, X.5
  • 5
    • 34547167635 scopus 로고    scopus 로고
    • Leakage power reduction of embedded memories on fpgas through location assignment
    • Y. Meng, T. Sherwood, and R. Kastner, "Leakage power reduction of embedded memories on fpgas through location assignment," in DAC, pp. 612-617, 2006.
    • (2006) DAC , pp. 612-617
    • Meng, Y.1    Sherwood, T.2    Kastner, R.3
  • 6
    • 34547174370 scopus 로고    scopus 로고
    • Optimality study of resource binding with multi-vdds
    • D. Chen, J. Cong, Y. Fan, and J. Xu, "Optimality study of resource binding with multi-Vdds," in DAC, pp. 580-585, 2006.
    • (2006) DAC , pp. 580-585
    • Chen, D.1    Cong, J.2    Fan, Y.3    Xu, J.4
  • 7
    • 34250765870 scopus 로고    scopus 로고
    • Timing-constraint and voltage-islandaware voltage assignment
    • H. Wu, M. Wong, and I. Liu, "Timing-constraint and voltage-islandaware voltage assignment," in DAC, pp. 429-432, 2006.
    • (2006) DAC , pp. 429-432
    • Wu, H.1    Wong, M.2    Liu, I.3
  • 8
    • 0036056702 scopus 로고    scopus 로고
    • Task scheduling and voltage selection for energy minimization
    • Y. Zhang, X. Hu, and D. Z. Chen, "Task scheduling and voltage selection for energy minimization," in DAC, pp. 183-188, 2002.
    • (2002) DAC , pp. 183-188
    • Zhang, Y.1    Hu, X.2    Chen, D.Z.3
  • 9
    • 0036396948 scopus 로고    scopus 로고
    • Impact of scaling on the effectiveness of dynamic power reduction schemes
    • D. Duarte, N. Vijaykrishnan, M. J. Irwin, H.-S. Kim, and G. Mc-Farland, "Impact of scaling on the effectiveness of dynamic power reduction schemes," in ICCD, pp. 382-387, 2002.
    • (2002) ICCD , pp. 382-387
    • Duarte, D.1    Vijaykrishnan, N.2    Irwin, M.J.3    Kim, H.-S.4    Mc-Farland, G.5
  • 10
    • 0042090422 scopus 로고    scopus 로고
    • Energy reduction techniques for multimedia applications with tolerance to deadline misses
    • S. Hua, G. Qu, and S. S. Bhattacharyya, "Energy reduction techniques for multimedia applications with tolerance to deadline misses," in DAC, pp. 131-136, 2003.
    • (2003) DAC , pp. 131-136
    • Hua, S.1    Qu, G.2    Bhattacharyya, S.S.3
  • 12
    • 47249142497 scopus 로고    scopus 로고
    • Minimizing leakage energy with modulo scheduling for VLIW DSP processors
    • Sep.
    • M. Wang, Z. Shao, H. Liu, and C. Xue, "Minimizing leakage energy with modulo scheduling for VLIW DSP processors," in DIPES, pp. 111-120, Sep. 2008.
    • (2008) DIPES , pp. 111-120
    • Wang, M.1    Shao, Z.2    Liu, H.3    Xue, C.4
  • 13
    • 38149039432 scopus 로고    scopus 로고
    • Real-time loop scheduling with energy optimization via dvs and abb for multi-core embedded systems
    • Dec.
    • G. Hua, M. Wang, Z. Shao, H. Liu, and C. Xue, "Real-time loop scheduling with energy optimization via dvs and abb for multi-core embedded systems," in EUC, pp. 1-12, Dec. 2007.
    • (2007) EUC , pp. 1-12
    • Hua, G.1    Wang, M.2    Shao, Z.3    Liu, H.4    Xue, C.5
  • 14
    • 0036917242 scopus 로고    scopus 로고
    • Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
    • S. Martin, K. Flautner, T. Mudge, and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in ICCAD, pp. 721-725, 2002.
    • (2002) ICCAD , pp. 721-725
    • Martin, S.1    Flautner, K.2    Mudge, T.3    Blaauw, D.4
  • 15
    • 4444368993 scopus 로고    scopus 로고
    • Leakage aware dynamic voltage scaling for real-time embedded systems
    • R. Jejurikar, C. Pereira, and R. Gupta, "Leakage aware dynamic voltage scaling for real-time embedded systems," in DAC, pp. 275-280, 2004.
    • (2004) DAC , pp. 275-280
    • Jejurikar, R.1    Pereira, C.2    Gupta, R.3
  • 16
    • 0021477994 scopus 로고
    • Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
    • H. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE Journal of Solid- State Circuits, vol. 19, pp. 468-473, 1984.
    • (1984) IEEE Journal of Solid- State Circuits , vol.19 , pp. 468-473
    • Veendrick, H.1
  • 17
    • 0029349967 scopus 로고
    • Static scheduling for synthesis of DSP algorithms on various models
    • L.-F. Chao and E. H.-M. Sha, "Static scheduling for synthesis of DSP algorithms on various models," Journal of VLSI Signal Processing Systems, vol. 10, pp. 207-223, 1995.
    • (1995) Journal of VLSI Signal Processing Systems , vol.10 , pp. 207-223
    • Chao, L.-F.1    Sha, E.H.-M.2
  • 18
    • 33746763910 scopus 로고
    • Retiming synchronous circuitry
    • C. E. Leiserson and J. B. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, pp. 5-35, 1991.
    • (1991) Algorithmica , vol.6 , pp. 5-35
    • Leiserson, C.E.1    Saxe, J.B.2
  • 19
    • 33947287207 scopus 로고    scopus 로고
    • Voltage assignment with guaranteed probability satisfying timing constraint for real-time multiproceesor DSP
    • M. Qiu, Z. Jia, C. Xue, Z. Shao, and E. H.-M. Sha, "Voltage assignment with guaranteed probability satisfying timing constraint for real-time multiproceesor DSP," Journal of VLSI Signal Processing Systems, vol. 46, pp. 55-73, 2007.
    • (2007) Journal of VLSI Signal Processing Systems , vol.46 , pp. 55-73
    • Qiu, M.1    Jia, Z.2    Xue, C.3    Shao, Z.4    Sha, E.H.-M.5
  • 20
    • 0003882780 scopus 로고    scopus 로고
    • Ph.D. dissertation, Dept. of Elect. Eng. and Comput. Sci., Univ. of California, Berkeley
    • T. Burd, Energy-Efficient processor system design. Ph.D. dissertation, Dept. of Elect. Eng. and Comput. Sci., Univ. of California, Berkeley, 2000.
    • (2000) Energy-Efficient Processor System Design
    • Burd, T.1


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