On the (Dis)similarity of transactional memory workloads

Proceedings of the 2009 IEEE International Symposium on Workload Characterization, IISWC 2009

Volumn , Issue , 2009, Pages 108-117

  Hughes, Clay ^a   Poe, James ^a   Qouneh, Amer ^a   Li, Tao ^a  

^a UNIVERSITY OF FLORIDA   (United States)

Author keywords

Performance analysis; Transactional memory

Indexed keywords

CONCURRENT PROGRAMMING; DESIGN EVALUATION; DESIGN PROCESS; FEATURE SUBSET; MICROBENCHMARKS; MULTI-CORE SYSTEMS; MULTITHREADED; PERFORMANCE ANALYSIS; PRINCIPLE COMPONENT ANALYSIS; PROGRAMMING MODELS; RUNTIMES; SOFTWARE ENGINEERS; TRANSACTIONAL MEMORY; WORKLOAD CHARACTERISTICS; WORKLOAD CHARACTERIZATION;

CLUSTERING ALGORITHMS; COMPUTER SOFTWARE SELECTION AND EVALUATION; COMPUTER SYSTEMS PROGRAMMING; DESIGN; SIMULATORS;

STORAGE ALLOCATION (COMPUTER);

EID: 70649095417     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2009.5306790     Document Type: Conference Paper

References (25)

1. R. H. Saavedra and A. J. Smith, "Analysis of Benchmark Characteristics and Benchmark Performance Prediction, " ACM Trans. Computer Systems, 1996.
2. L. Eeckhout, H. Vandierendonck, and K. De Bosschere, "Quantifying The Impact of Input Data Sets On Program Behavior and Its Applications, " Journal of Instruction Level Parallelism, 2003.
3. M. Herlihy and J.E. Moss, "Transactional Memory: Architectural Support For Lock-free Data Structures, " In Proceedings of International Symposium on Computer Architecture, 1993.
4. J. Bobba, K. Moore, L. Yen, H. Volos, M. Hill, M. Swift, and D. Wood, "Performance Pathologies in Hardware Transactional Memory, " In Proceedings of the International Symposium on Computer Architecture, 2007.
5. A. McDonald, J. Chung, H. Chafi, C. C. Minh, B. Barlstrom, L. Hammond, C. Kozyrakis and K. Olukotun, "Characterization of TCC on Chip-Multiprocessors, " In Proceedings of International Conference on Parallel Architectures and Compilation Techniques, 2005.
6. C. H. Romesburg, "Cluster Analysis for Researchers" Lifetime Learning Publications, 1984.
7. SESC: A Simulator of Superscalar Multiprocessors and Memory Systems with Thread-Level Speculation Support, http://sourceforge.net/projects/sesc.
8. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations, " In Proceedings of International Symposium on Computer Architecture, 1995.
9. C. C. Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun, "An Effective Hybrid Transactional Memory System With Strong Isolation Guarantees, " In Proceedings of International Symposium on Computer Architecture, 2007.
10. C. Bienia, S. Kumar, J.P. Singh, and K. Li, "The PARSEC Benchmark Suite: Characterization and Architectural Implications, " Princeton University Technical Report, 2008.
11. StatSoft, Inc, STATISTICA. http://www.statsoft.com.
12. M. Hughes, "Exploration and Play Re-visited: A Hierarchical Analysis, " International Journal of Behavioral Development, 1979.
13. L. Eeckhout, H. Vandierendonck, and K. De Bosschere, "Designing Computer Architecture Research Workloads, " Computer, 36, 2, pp. 65- 71, 2003.
14. H. Vandierendonck and K. Bosschere, "Many Benchmarks Stress the Same Bottlenecks, " In Proceedings of the Workshop on Computer Architecture Evaluation Using Commercial Workloads, 2004.
15. A. Phansalkar, A. Joshi, and L. K. John, "Analysis of Redundancy And Application Balance In The SPEC CPU2006 Benchmark Suite, " In Proceedings of International Symposium on Computer Architecture, 2007.
16. J. Chung, H.Chafi, A. McDonald, C. C. Minh, B. Carlstrom, C. Kozyrakis, and K. Olukotun, "The Common Case Transactional Behavior of Multithreaded Programs, " In Proceedings of International Conference on High Performance Computer Architecture, 2006.
17. L. Hammond, et. al., "Transactional Memory Coherence and Consistency, " In Proceedings of the International Symposium on Computer Architecture. 2004.
18. C. Ananian, K. Asanovic, B. Kuszmaul, C. Leiserson, and S. Lie, "Unbounded Transactional Memory, " In Proceedings of the International Conference on High Performance Computer Architecture, 2005.
19. R. Rajwar, M. Herlihy, and K. Lai, "Virtualizing Transactional Memory, " In Proceedings of International Symposium on Computer Architecture, 2005.
20. K. P. Eswaran, J. N. Gray, R. A. Lorie, and I. L. Traiger, "The Notions Of Consistency And Predicate Locks In A Database System, " Communications ACM 19, 1976.
21. K. Moore, J. Bobba, M. Moravan, M. Hill, and D. Wood, "LogTM: Logbased Transactional Memory, " In Proceedings of the International Symposium on High-Performance Computer Architecture, 2006.
22. C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun, "STAMP: Standford Transactional Memory Applications for Multi-Processsing, " In Proceedings of International Symposium on Workload Characterization, 2008.
23. C. Bienia, S. Kumar, and K. Li, "PARSEC vs. SPLASH-2: A Quantitative Comparison of Two Multithreaded Benchmark Suites on Chip-Multiprocessors, " In Proceedings of International Symposium on Workload Characterization, 2008.
24. G.H. Dunteman, "Principal Component Analysis, " Newbury Park, California: Sage, 1989.
25. J. Poe, C. Cho, and T. Li., "Using Analytical Models to Efficiently Explore Hardware Transactional Memory And Multi-core Co-design, " In Proceedings of International Symposium on Computer Architecture and High Performance Computing, 2008.