Schottky barrier height modulation of nickeldysprosium-alloy germanosilicide contacts for strained P-FinFETs

IEEE Electron Device Letters

Volumn 30, Issue 12, 2009, Pages 1278-1280

  Sinha, Mantavya ^a   Lee, Rinus Tek Po ^a   Chor, Eng Fong ^a   Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Aluminum implant; Contact resistance; FinFETs; Nickel (Ni) dysprosium (Dy) alloy germanosilicide (NiDySiGe); Schottky barrier height

Indexed keywords

FINFETS; GERMANOSILICIDE; SCHOTTKY BARRIER HEIGHT; SCHOTTKY BARRIER HEIGHTS;

ALUMINUM; CONTACT RESISTANCE; DYSPROSIUM; NICKEL; NICKEL ALLOYS; SCHOTTKY BARRIER DIODES; SEMICONDUCTING GERMANIUM COMPOUNDS; SEMICONDUCTOR METAL BOUNDARIES; SILICIDES; SILICON ALLOYS;

DYSPROSIUM ALLOYS;

EID: 70549083809     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2034111     Document Type: Article

References (17)

1. A. M. Noori, M. Balseanu, P. Boelen, A. Cockburn, S. Demuynck, S. Felch, S. Gandikota, A. J. Gelatos, A. Khandelwal, J. A. Kittl, A. Lauwers, W.-C. Lee, J. Lei, T. Mandrekar, R. Schreutelkamp, K. Shah, S. E. Thompson, P. Verheyen, C.-Y. Wang, L.-Q. Xia, and R. Arghavani, "Manufacturable processes for for 32-nm-node CMOS enhancement by synchronous optimization of strain-engineered channel and external parasitic resistances, IEEE Trans. Electron Devices 55 5 1259-1264 May 2008.
2. S.-D. Kim, S. Narasimha, and K. Rim, "An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs," in IEDM Tech Dig., 2005, pp. 149-152.
3. Semicond. Ind. Assoc, The International Technology Roadmap for Semiconductors (ITRS), San Jose, CA, 2007.
4. H. Shang, L. Chang, X. Wang, M. Rooks, Y. Zhang, B. To, K. Babich, G. Totir, Y Sun, E. Kiewra, M. Ieong, and W Haensch, "Investigation of FinFET devices for 32 nm technologies and beyond," in VLSISymp. Tech. Dig., 2006, pp. 54-55.
5. N. Collaert, R. Rooyackers, A. Hikavyy, A. Dixit, F. Leys, P. Verheyen, R. Loo, M. Jurczak, and S. Biesemans, "Multi-gate devices for the 32 nm technology node and beyond: Challenges for selective epitaxial growth," Thin Solid Films, vol.517, no.1, pp. 101-104, Nov. 2008.
6. T.-Y Liow, K.-M. Tan, D. Weeks, R. T. P. Lee, M. Zhu, K.-M. Hoe, C.-H. Tung, M. Bauer, J. Spear, S. G. Thomas, G. S. Samudra, N. Balasubramanian, and Y.-C. Yeo, "Strained n-channel FinFETs featuring in situ doped silicon-carbon (Sii-yCy) source and drain stressors with high carbon content," IEEE Trans. Electron Devices, vol.55, no.9, pp. 2475-2483, Sep. 2008.
7. P. Verheyen, N. Collaert, R. Rooyackers, R. Loo, D. Shamiryan, A. De Keersgieter, G. Eneman, F. Leys, A. Dixit, M. Goodwin, Y. S. Yim, M. Caymax, K. De Meyer, P. Absil, M. Jurczak, and S. Biesemans, "25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Sio.sGeo. 2 in the source and drain regions," in VLSI Symp. Tech. Dig., 2005, pp. 194-195.
8. J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau, "Tri-gate transistor architecture with high-fc gate dielectrics, metal gates and strain engineering," in VLSI Symp. Tech. Dig., 2006, pp. 50-51.
9. K.-M. Tan, T.-Y. Liow, R. T. P. Lee, K. M. Hoe, C.-H. Tung, N. Balasubramanian, G. S. Samudra, and Y.-C. Yeo, "Strained p-channel FinFETs with extended Π-shaped silicon-germanium source and drain stressors," IEEE Electron Device Lett., vol.28, no.10, pp. 905-908, Oct. 2007. (Pubitemid 47521573)
10. A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. D. Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol.52, no.6, pp. 1132-1140, Jun. 2005.
11. K. Maex and M. Van Rossum, Properties of Metal Silicides. London, U.K.: IEE-INSPEC, 1995.
12. R. T. P. Lee, A. T.-Y. Koh, F.-Y Liu, W.-W Fang, T.-Y. Liow, K.-M. Tan, P.-C. Lim, A. E.-J. Lim, M. Zhu, K.-M. Hoe, C.-H. Tung, G.-Q. Lo, X. Wang, D. K.-Y Low, G. S. Samudra, D.-Z. Chi, and Y.-C. Yeo, "Route to low parasitic resistance in MuGFETs with silicon-carbon source/drain: Integration of novel low barrier Ni(M)Si:C metal silicides and pulsed laser annealing," in IEDM Tech Dig., 2007, pp. 685-688.
13. S.-L. Zhang, "Nickel-based contact metallization for SiGe MOSFETs: Progress and challenges," Microelectron. Eng., vol.70, no.2-4, pp. 174-185, Nov. 2003.
14. M. Sinha, R. T. P. Lee, A. Lohani, S. Mhaisalkar, E. F. Chor, and Y.-C. Yeo, "Achieving sub-0.1 eV hole Schottky barrier height for NiSiGe on SiGe by aluminum segregation," J. Electrochem. Soc, vol.156, no.4, pp. 233-238, Jan. 2009.
15. D. K. Schroder, Semiconductor Material and Device Characterization, 3rd ed. New York: IEEE Press, 2006.
16. E. Dubois and G. Larrieu, "Measurement of low Schottky barrier heights applied to metallic source/drain metal-oxide-semiconductor field effect transistors," J. Appl. Phys., vol.96, no.1, pp. 729-737, Jul. 2004.
17. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.